Power efficient level one data cache access with pre-validated tags

A computer system, comprising:

• a processor including a processing core to execute a memory access instruction indicating a virtual memory address;
• a cache memory;
• a memory controller, accessible to the processor, including a page table to translate virtual memory addresses to corresponding physical memory addresses;
• memory, accessible to the processor, via the memory controller;
• and
• an I/O hub, accessible to the processor, to provide I/P interfaces to communicate with I/O devices;
• wherein the cache memory includes:
• a translation lookaside buffer (TLB) including a TLB tag array and a TLB content array, the TLB tag array and TLB content array each including a plurality of TLB sets, each TLB set associated with a group of way entries;
• a cache array including a level 1 (L1) tag array and a cache content array, the L1 tag array and cache content array each including a plurality of cache array sets, each cache array set associated with a group of way entries;
• and
• tag structure logic to:
• store TLB vectors in the L1 tag array, wherein the TLB vectors identify an entry of the TLB content array containing a portion of a physical memory address corresponding to the virtual memory address;
• generate TLB vectors responsive to receiving virtual memory addresses that hit in the TLB tag array;
• and
• compare a generated TLB vector with a TLB vector stored in the L1 tag array to determine a cache hit.

A processor, comprising:

• a processing core to execute a memory access instruction associated with a virtual memory address;
• a core cache memory, accessible to the processor, including:
• a set associative, multiple way translation lookaside buffer (TLB) including a TLB tag array and a TLB content array;
• and
• a set associative, multiple way cache array including a level 1 (L1) tag array and a cache content array;
• and
• tag structure logic to:
• determine a TLB set associated with the virtual memory address;
• compare a TLB tag portion of the virtual memory address with TLB tags stored in way entries of the TLB tag array, wherein the way entries are associated with the TLB set;
• generate, when the TLB tag portion matches a TLB tag stored in one of the way entries, a TLB vector indicative of the TLB set and the way entry that matched;
• identify a set in a L1 tag array based on the virtual memory address;
• compare the TLB vector with stored TLB vectors stored in way entries of the L1 tag array, wherein the L1 tag array way entries are associated with the L1 tag array set;
• and
• generate, when the TLB vector matches a stored TLB vector in one of the L1 tag array way entries, a way select output indicative of the L1 tag array set and the L1 tag array way entry that matched.

The processor of 15, wherein the tag structure logic is operable to allocate a TLB entry when the TLB tag portion does not match any of the TLB tags stored in the way entry, wherein the tag structure logic is operable to:

• identify one of the way entries;
• store the TLB tag portion of the virtual memory address in a TLB tag array entry associated with the TLB set and the way entry identified;
• obtain a physical memory address associated with the virtual memory address;
• and
• store a portion of the physical memory address in an entry of a TLB data array, wherein the TLB data array entry is associated with the TLB set and the way entry identified.