Method for reliably addressing a large flash memory and flash memory

A flash memory for a host system, comprising:

• a controller;
• a volatile cache memory connected to said controller;
• and
• a multiplicity of memory blocks which can be erased in a respective erase process and connected to said controller, said memory blocks being subdivided into memory pages which can be written to in a respective write process and each memory page also being subdivided into partial pages and each partial page having a physical partial page address which can be assigned logical sector addresses which can be addressed by the host system, physical partial page addresses assigned to the logical sector addresses being able to be determined using hierarchically organized structures of address tables for converting the logical sector addresses into the physical partial page addresses, the address tables having a size of a partial memory page, said multiplicity of memory blocks divided into areas which contain at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for said memory blocks, and a logbook area, and the physical partial page addresses of said static area and of said write area can be determined from the logical sector addresses using a useful data address table structure, the physical partial page addresses of said block management area can be determined using a block management address table structure, and changes to the address tables can be recorded in said volatile cache memory and in partial memory pages of said logbook area.