Power reduction in server memory system

A computer system having a host processor device running an operating system, a memory including multiple memory chips having physical memory locations grouped into ranks, and a memory controller interfacing the host processor device with the memory, the host processor device in communication with said memory controller adapted to perform a method comprising:

• maintaining, by the memory controller, a mapping of said ranks to physical memory addresses in said memory chips, said memory controller servicing memory access requests at address locations mapped to physical memory locations within a rank;
• monitoring usage of memory address locations in each said rank, the monitoring comprising:
• mapping, at said memory controller, for association with a respective single rank, two or more performance counters for monitoring memory access usage level at a respective two or more sub-sections of physical memory locations within the respective single rank;
• incrementing, at a respective performance counter of said two or more performance counters associated with a single rank, a respective count value for each physical memory location accessed within a respective sub-section;
• and
• comparing, for each respective rank, a count value of each respective counter against a first threshold indicating a first host memory usage level below which that respective rank can be powered off;
• identifying, responsive to said comparing, one or more ranks indicating usage at or above said first host memory usage level;
• and
• moving data from memory locations of the identified rank over said bus to another rank indicating usage above said first host memory usage level to thereby eliminate usage of the identified rank,
• wherein execution of a program running on said host processor device is suspended prior to said moving;
• and
• powering off the memory chip having the said identified rank.