Method and system for thread monitoring
AssigneeAdvanced Micro Devices, Inc.
InventorBrian D. Emberling
Life of this patent
Estimating the term…
Abstract
An apparatus and methods for hardware-based performance monitoring of a computer system are presented. The apparatus includes: processing units; a memory; a connector device connecting the processing units and the memory; probes inserted the processing units, and the probes generating probe signals when selected processing events are detected; and a thread trace device connected to the connector device. The thread trace device includes an event interface to receive probe signals, and an event memory controller to send probe event messages to the memory, where probe event messages are based on probe signals. The probe event messages transferred to memory can be subsequently analyzed using a software program to determine, for example, thread-to-thread interactions.
Claims19
A method for monitoring performance of a computer system, the method comprising:
- inserting one or more hardware probes in at least one processing unit, wherein the hardware probes are configured to generate probe signals in response to detecting predetermined processing events;
- configuring a hardware-based device to:
- receive the probe signals from the hardware probes;
- store probe event messages for the received probe signals in an event memory in the hardware-based device;
- transfer the probe event messages from the event memory to a memory external to the hardware-based device via a first-in-first-out buffer;
- provide feedback to the hardware-based thread trace device wherein the feedback includes a current measure of accesses to the memory external to the hardware based device;
- and
- regulate a frequency of the transfer of the probe event messages from the event memory based on the feedback.
An apparatus for monitoring the performance of a computer system, comprising:
- one or more processing units;
- a memory;
- a connector device connecting the one or more processing units and the memory;
- one or more hardware probes included in at least one of the processing units and configured to generate probe signals in response to detecting predetermined processing events;
- a hardware-based thread trace device connected to the connector device, the thread trace device including (i) an event memory, (ii) an event interface configured to receive the probe signals from the hardware probes and to store probe event messages for the received probe signals in the event memory, and (iii) an event memory buffer controller configured to send probe event messages from the event memory to the memory;
- a memory controller device configured to transfer the probe event messages from the hardware-based thread trace device to the memory via a first-in-first-out buffer;
- and
- the memory controller device further configured to provide feedback to the hardware-based thread trace device, the feedback including a current measure of accesses to the memory,
- wherein the hardware-based thread trace device is configured to regulate a frequency of the transfer of the probe event messages from the event memory based on the feedback.
Dependencies are inferred from the claim text.