Semiconductor storage circuit and operation method thereof

An operation method of a semiconductor storage circuit including a memory core having a plurality of memory cells, the operation method comprising:

• activating the memory core in response to input of a command for each operation cycle;
• when a write command is input as the command for a first operation cycle of the each operation cycle, performing error checking and correction (ECC) encoding of input data which has been input for the first operation cycle and thus generating ECC data, and generating write data comprising the input data and the ECC data;
• writing the write data into a memory cell addressed by a write address which has been input for the first operation cycle during the activation of the memory core;
• when a read command is input as the commend for a second operation cycle of the each operation cycle, reading data to be read from a memory cell addressed by a read address which has been input for the second operation cycle;
• performing ECC decoding of the thus read data using ECC data included in the read data and thus generating output data;
• and
• making an adjustment to equalize a delay from input of the write command until activation of the memory core and a delay from input of the read command until activation of the memory core, by one of:
• a delay circuit that makes the adjustment by generating a delayed clock by delaying a clock signal which is supplied from outside the semiconductor storage circuit, and supplying the delayed clock to the memory core, the ECC decoding being performed in sync with the delayed clock and a delay time of the delayed clock being set such that activation of the memory core will follow completion of the ECC encoding;
• and
• a control circuit that makes the adjustment by generating a control signal for controlling an activation of the memory core, and supplying the control signal to the memory core.