Controlling memory access conflict of threads on multi-core processor with set of highest priority processor cores based on a threshold value of issued-instruction efficiency
AssigneeFujitsu Limited
InventorsKoichiro Yamashita, Hiromasa Yamauchi, Kiyoshi Miyazaki
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Abstract
A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
Claims6
A multi-core processor system comprising a plurality of cores and memory accessible from the cores, wherein a given core is configured to:
- detect among the cores, first cores having a highest execution priority level,
- calculate an issued-instruction efficiency of each of the first cores by dividing a cycle count for the first core by an issued instruction count for the first core,
- identify among the detected first cores, a second core accessing the memory and having the issued-instruction efficiency greater than a given threshold, and
- control a third core accessing the memory and thereby causing an access conflict with the second core, to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
A thread control method of a multi-core processor system comprising a plurality of cores and memory accessible from the cores, the thread control method being executed by the cores and comprising:
- detecting among the cores, first cores having a highest execution priority level;
- calculating an issued-instruction efficiency of each of the first cores by dividing a cycle count for the first core by an issued instruction count for the first core;
- identifying among the detected first cores, a second core accessing the memory and having the issued-instruction efficiency greater than a given threshold;
- and
- instructing control of a third core accessing the memory and thereby causing an access conflict with the second core, to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
A non-transitory computer-readable recording medium storing a control program causing a plurality of cores in a multi-core processor system comprising the cores and memory accessible from the cores, to execute a process, the process comprising:
- detecting among the cores, first cores having a highest execution priority level;
- calculating an issued-instruction efficiency of each of the first cores by dividing a cycle count for the first core by an issued instruction count for the first core;
- identifying among the detected first cores, a second core accessing the memory and having the issued-instruction efficiency greater than a given threshold;
- and
- instructing control of a third core accessing the memory and thereby causing an access conflict with the second core, to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
Dependencies are inferred from the claim text.