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US 9,311,137 B2Granted
Delaying interrupts for a transactional-execution facility
AssigneeInternational Business Machines Corporation
InventorsGuenter Gerwig, Christian Jacobi, Frank Lehnert
Life of this patent
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Abstract
A mechanism is provided for completing of set of instructions while receiving interrupts. The mechanism executes a set of instructions. Responsive to receiving an interrupt and determining that the interrupt requires processing within an implementation time frame, the mechanism delays the interrupt for a predetermined time period. Responsive to completing the set of instructions within the predetermined time period, the mechanism processes the interrupt.
Claims20
A method implemented by a data processing system, for executing a set of instructions while receiving interrupts, the method comprising:
- executing a set of instructions;
- receiving an interrupt;
- responsive to determining that the interrupt fails to have an implementation time frame, suspending processing of the interrupt for a predetermined time period;
- responsive to completing the set of instructions within the predetermined time period, processing the interrupt;
- responsive to determining that the interrupt has an implementation time frame, determining whether a delay mode is active;
- responsive to the delay mode being active, delaying processing of the interrupt, thereby forming a delayed interrupt, and setting keeper logic in order to maintain a state for the delayed interrupt;
- starting a delay counter that incremented on every processor cycle;
- on every clock cycle:
- determining whether the delay counter has reached a predetermined delay threshold;
- responsive to the delay counter failing to have reached the predetermined delay threshold, determining whether the set of instructions has completed execution;
- responsive to the set of instructions completing execution, processing the delayed interrupt;
- responsive to the set of instructions failing to have completed execution, incrementing the delay counter;
- and
- responsive to the delay counter reaching the predetermined delay threshold, processing the delayed interrupt and aborting the set of instructions;
- and
- responsive to the delay mode failing to be active, processing the delayed interrupt and aborting the set of instructions.
13 more elements
A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
- execute a set of instructions;
- receive an interrupt;
- responsive to determining that the interrupt fails to have an implementation time frame, suspend processing of the interrupt for a predetermined time period;
- and
- responsive to completing the set of instructions within the predetermined time period, process the interrupt
- responsive to determining that the interrupt implementation time frame, determine whether a delay mode is active;
- responsive to the delay mode being active, delay processing of the interrupt, thereby forming a delayed interrupt, and set keeper logic in order to maintain a state for the delayed interrupt;
- start a delay counter that is incremented on every processor cycle;
- on every clock cycle:
- determine whether the delay counter has reached a predetermined delay threshold;
- responsive to the delay counter failing to have reached the predetermined delay threshold, determine whether the set of instructions has completed execution;
- responsive to the set of instructions completing execution, process the delayed interrupt;
- responsive to the set of instructions failing to have completed execution, increment the delay counter;
- and
- responsive to the delay counter reaching the predetermined delay threshold, process the delayed interrupt and aborting the set of instructions;
- and
- responsive to the delay mode failing to be active, process the delayed interrupt and aborting the set of instructions.
14 more elements
An apparatus, comprising:
- a processor;
- and
- a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
- execute a set of instructions;
- receive an interrupt;
- responsive to determining that the interrupt fails to have an implementation time frame, suspend processing of the interrupt for a predetermined time period;
- and
- responsive to completing the set of instructions within the predetermined time period, process the interrupt
- responsive to determining that the interrupt has an implementation time frame, determine whether a delay mode is active;
- responsive to the delay mode being active, delay processing of the interrupt, thereby forming a delayed interrupt, and set keeper logic in order to maintain a state for the delayed interrupt;
- start a delay counter that s incremented on every processor cycle;
- on every clock cycle:
- determine whether the delay counter has reached a predetermined delay threshold;
- responsive to the delay counter failing to have reached the predetermined delay threshold, determine whether the set of instructions has completed execution;
- responsive to the set of instructions completing execution, process the delayed interrupt;
- responsive to the set of instructions failing to have completed execution, increment the delay counter;
- and
- responsive to the delay counter reaching the predetermined delay threshold, process the delayed interrupt and aborting the set of instructions;
- and
- responsive to the delay mode failing to be active, process the delayed interrupt and aborting the set of instructions.
17 more elements
Dependencies are inferred from the claim text.