Managing per-tile event count reports in a tile-based architecture
AssigneeNVIDIA Corporation
InventorsZiyad S. Hakura, Jerome F. Duluk, Jr.
Life of this patent
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AssigneeNVIDIA Corporation
InventorsZiyad S. Hakura, Jerome F. Duluk, Jr.
Estimating the term…
A graphics processing system configured to track per-tile event counts in a tile-based architecture. A tiling unit in the graphics processing system is configured to cause a screen-space pipeline to load a count value associated with a first cache tile into a count memory and to cause the screen-space pipeline to process a first set of primitives that intersect the first cache tile. The tiling unit is further configured to cause the screen-space pipeline to store a second count value in a report memory location. The tiling unit is also configured to cause the screen-space pipeline to process a second set of primitives that intersect the first cache tile and to cause the screen-space pipeline to store a third count value in the first accumulating memory. Conditional rendering operations may be performed on a per-cache tile basis, based on the per-tile event count.
A graphics processing system configured to track per-tile event counts in a tile-based architecture, the graphics processing system comprising:
A computing device configured to track per-tile event counts in a tile-based architecture, the computing device comprising:
A method for tracking per-tile event counts in a tile-based architecture, the method comprising:
Dependencies are inferred from the claim text.