Predicting a pattern in addresses for a memory-accessing instruction when processing vector instructions

A processor that executes vector instructions, comprising:

• a load/store unit including a first pipeline configured to perform a first version of a memory operation and a second pipeline configured to perform a second version of the memory operation, wherein the first pipeline is configured to access multiple vector elements in parallel and the second pipeline is configured to access each vector element separately, wherein the load/store unit is configured to:
• encounter a vector memory-accessing instruction that performs the memory operation for a set of elements in the memory-accessing instruction;
• and
• for each active element in the memory-accessing instruction, upon determining that addresses in the elements are likely to be arranged in a predetermined pattern of addresses:
• predict that the addresses in the elements are arranged in the predetermined pattern;
• determine at least one specified element of the memory accessing instruction based on the predetermined pattern;
• generate the first version of the memory operation based on the predetermined pattern, the generating comprising performing an address translation for a single address from the at least one specified element to determine a single physical address and using the single physical address and the predetermined pattern to determine one or more other addresses for the first version of the memory operation;
• and
• perform the first version of the memory operation in the first pipeline.

A computer system that executes vector instructions, comprising:

• a memory that stores instructions and data for a processor;
• and
• the processor coupled to the memory, the processor including:
• a load/store unit including a first pipeline configured to perform a first version of a memory operation and a second pipeline configured to perform a second version of the memory operation, wherein the first pipeline is configured to access multiple vector elements in parallel and the second pipeline is configured to access each vector element separately, wherein the load/store unit is configured to:
• encounter a vector memory-accessing instruction that performs the memory operation for a set of elements in the memory-accessing instruction;
• and
• for each active element in the memory-accessing instruction, upon determining that addresses in the elements are likely to be arranged in a predetermined pattern of addresses:
• predict that the addresses in the elements are arranged in the predetermined pattern;
• determine at least one specified element of the memory accessing instruction based on the predetermined pattern;
• generate the first version of the memory operation based on the predetermined pattern, the generating comprising performing an address translation for a single address from the at least one specified element to determine a single physical address and using the single physical address and the predetermined pattern to determine one or more other addresses for the first version of the memory operation;
• and
• perform the first version of the memory operation in the first pipeline.