Indirect instruction predication

A circuit arrangement, comprising:

• a processing unit;
• a first register disposed in the processing unit;
• a second register disposed in the processing unit;
• an execution unit disposed in the processing unit and configured to receive a predication enable signal that indicates whether to predicate an instruction and selectively predicate instructions based at least in part on the predication enable signal;
• and
• predication logic disposed in the processing unit and configured to receive a first register address corresponding to the first register included in the instruction, determine a second register address based at least in part on a value stored at the first register address of the first register, and communicate the predication enable signal based at least in part on a value stored at the second register address, wherein the second register address corresponds to the second register, wherein the first register includes a plurality of register entries and the first register address of the instruction points to a particular register entry of the plurality of register entries of the first register, and wherein each register entry of the first register points to a bit location of the second register, the second register address comprises the bit location of the second register pointed to by the particular register entry corresponding to the first register address, and the predication logic is configured to communicate the predication enable signal based at least in part on a value stored at the second register address by retrieving the value stored at the bit location pointed to by second register address.