US 9,311,084 B2 · RDA checkpoint optimization

Abstract

A system and method for efficiently performing microarchitectural checkpointing. A register rename unit within a processor determines whether a physical register number qualifies to have duplicate mappings. Information for maintenance of the duplicate mappings is stored in a register duplicate array (RDA). To reduce the penalty for misspeculation or exception recovery, control logic in the processor supports multiple checkpoints. The RDA is one of multiple data structures to have checkpoint copies of state. The RDA utilizes a content addressable memory (CAM) to store physical register numbers. The duplicate counts for both the current state and the checkpoint copies for a given physical register number are updated when instructions utilizing the given physical register number are retired. To reduce on-die real estate and power consumption, a single CAM entry is stores the physical register number and the other fields are stored in separate storage elements.

Claims14

Dependent claims

A processor comprising:

a decoder configured to decode fetched instructions;
a register rename unit;
and
wherein the register rename unit is configured to:
receive decoded instructions;
determine to duplicate renaming assignments for a rename register identifier (ID) corresponding to a decoded move instruction;
allocate a plurality of entries corresponding to the given rename register ID;
maintain a duplicate count in at least a first entry of the plurality of entries for the given rename register ID;
wherein the given rename register ID is not stored in the plurality of entries;
and
wherein when a first checkpoint event has occurred:
allocate a given entry of the plurality of entries different from the first entry;
and
update the given entry with information stored in the first entry.

11 more elements

Dependencies are inferred from the claim text.

RDA checkpoint optimization

Life of this patent

RDA checkpoint optimization

Life of this patent

Abstract

Claims14