US 9,311,075 B2Granted

Electronic apparatus and BIOS updating apparatus thereof

AssigneeASMedia Technology Inc.

InventorsChih-Wei Hu, Lin-Hung Chen

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Abstract

An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS.

Claims10

Dependent claims

A basic input/output system (BIOS) updating apparatus suitable for an electronic apparatus which has a BIOS memory and a chipset, comprising:

a first interface circuit;
a volatile memory coupled to the first interface circuit, when an extended storage is connected to the first interface circuit, the chipset is in a disable mode, and a first BIOS in the extended storage is stored in the volatile memory by the first interface circuit;
a second interface circuit connected to the BIOS memory, wherein the BIOS memory has a second BIOS, wherein the first BIOS and the second BIOS are independent BIOSes;
and
a first switcher including three selection terminals, a first selection terminal coupled to the volatile memory, a second selection terminal coupled to the second interface circuit, and a common terminal coupled to the chipset, respectively;
wherein the BIOS memory and the extended storage are independent storages, and when the first BIOS is stored in the volatile memory, the volatile memory is coupled to the chipset by the first switcher;
when the first BIOS is not stored in the volatile memory, the second interface circuit is coupled to the chipset by the first switcher.

4 more elements

An electronic apparatus, comprising:

a central processing unit (CPU);
a chipset coupled to the CPU;
a first interface circuit;
a volatile memory coupled to the first interface circuit, when an extended storage is connected to the first interface circuit, then a first BIOS in the extended storage is stored in the volatile memory by the first interface circuit;
a BIOS memory having a second BIOS, wherein the first BIOS and the second BIOS are independent BIOSes;
a second interface circuit coupled to the BIOS memory;
a first switcher, a first selection terminal of the first switcher coupled to the volatile memory, a second selection terminal of the first switcher coupled to the second interface circuit, a common terminal of the first switcher coupled to the chipset, and;
a second switcher, a first selection terminal of the second switcher coupled to the first interface circuit, a second selection terminal of the second switcher coupled to the chipset, a common terminal of the second switcher couples to the extended storage;
when the chipset is in a normal mode, the extended storage is coupled to the chipset by the second switcher when the chipset is in a disable mode the extended storage is coupled to the first interface circuit by the second switcher,
wherein the BIOS memory and the extended storage are independent storages, and when the first BIOS is stored in the volatile memory, the volatile memory is coupled to the chipset by the first switcher;
when the first BIOS is not stored in the volatile memory, the second interface circuit is coupled to the chipset by the first switcher.

8 more elements

Dependencies are inferred from the claim text.