Memory with mixed cell array and system including the memory
AssigneeInternational Business Machines Corporation
InventorsBing Dai, Chung H. Lam, Jing Li
Life of this patent
Estimating the term…
Abstract
A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.
Claims17
A method of reducing memory system power consumption comprising:
- providing a plurality of memory units in a common memory space shared by a plurality of requesting devices, said plurality of memory units comprising:
- at least one performance memory unit storing a single bit per cell, and
- at least one dense memory unit storing a selected number of n bits in each cell, such that each performance memory unit consumes at least n times as much power per bit as each of said dense memory units;
- providing a memory controller allocating requested memory space in said plurality of memory units to a requesting device, said memory controller allocating dense memory and selectively including a performance memory portion, wherein for each request said memory controller allocates all dense memory, all performance memory, or a combination of dense memory and performance memory;
- and
- receiving a density indication from allocated memory with each memory access, said density indication indicating whether performance memory or dense memory is being accessed by a respective device.
A method of reducing system power consumption comprising:
- receiving a request for memory from one of a plurality of processing units;
- allocating memory from a plurality of memory units in a common memory space responsive to said request, said plurality of memory units comprising:
- at least one performance memory unit storing a single bit per cell, and
- at least one dense memory unit storing a selected number n of bits in each cell, each performance memory unit consuming at least n times as much power per bit as each of said dense memory units, wherein allocating either allocates all performance memory, all dense memory or a combination of performance memory and dense memory for each request, dense memory being allocated for data intensive threads and allocating selectively includes a performance memory portion;
- requesting access to allocated memory;
- and
- receiving a density indication from allocated memory with each memory access request, said density indication indicating whether said memory access request is for performance memory or dense memory.
A method of reducing system power consumption comprising:
- receiving a request for main memory space from one of a plurality of processing units sharing main memory;
- allocating space in main memory responsive to said request, said main memory including a plurality of storage class memory (SCM) units, said plurality of SCM units comprising:
- a plurality of Single-Level Cell (SLC) memory units storing a single bit per cell, and
- a plurality of Multi-Level Cell (MLC) memory units storing n of bits in each cell, each SLC memory unit consuming at least n times as much power per bit as each of said MLC memory units;
- requesting access to allocated memory;
- and
- receiving a density indication from allocated memory with each memory access request, said density indication indicating whether said memory access request is for SLC or MLC.
Dependencies are inferred from the claim text.