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US 9,310,866 B2Granted
Semiconductor device and alarm device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsJun Koyama, Shunpei Yamazaki
Life of this patent
Estimating the term…
Abstract
In the microcomputer in the alarm device, supply of power to a sensor portion or a CPU in a sensor is allowed or stopped by a power gate controlled by a power gate controller. In addition, a volatile memory portion and a nonvolatile memory portion are provided in the CPU, data of the volatile memory portion is stored in the nonvolatile memory portion before supply of power to the CPU is stopped, and the data of the nonvolatile memory portion is restored to the volatile memory portion after the supply of power to the CPU is resumed. Thus, during an interval between measurement periods, supply of power to the sensor portion and the CPU can be stopped, so that low power consumption can be achieved compared with the case where power is continuously supplied.
Claims28
A device comprising:
- a power gate controller electrically connected to a power supply line;
- a power gate electrically connected to the power supply line and the power gate controller;
- a CPU electrically connected to the power gate;
- and
- a sensor portion electrically connected to the power gate and the CPU,
- wherein the power gate controller comprises a timer and is configured to control the power gate with use of the timer,
- wherein the power gate is configured to allow or stop supply of power from the power supply line to the CPU and the sensor portion, in accordance with control by the power gate controller;
- wherein the sensor portion is configured to transmit a measurement value obtained by measuring a physical quantity to the CPU,
- wherein the CPU is configured to perform an arithmetic processing on the measurement value and transmit a signal based on an arithmetic result,
- wherein the CPU comprises a first memory portion and a second memory portion electrically connected to the first memory portion,
- wherein the first memory portion comprises a first transistor which comprises a first semiconductor,
- wherein the second memory portion comprises a second transistor which comprises a second semiconductor, the second semiconductor having a different band gap width from that of the first semiconductor, and
- wherein the CPU is configured to store data of the first memory portion in the second memory portion before the power gate stops the supply of power, and restore the data of the second memory portion to the first memory portion when the power gate allows to resume the supply of power.
10 more elements
An alarm device comprising a housing including a microcomputer,
- wherein the microcomputer comprises:
- a power gate controller electrically connected to a power supply line;
- a power gate electrically connected to the power supply line and the power gate controller;
- a CPU electrically connected to the power gate;
- and
- a sensor portion electrically connected to the power gate and the CPU,
- wherein the power gate controller comprises a timer and is configured to control the power gate with use of the timer,
- wherein the power gate is configured to allow or stop supply of power from the power supply line to the CPU and the sensor portion, in accordance with control by the power gate controller;
- wherein the sensor portion is configured to transmit a measurement value obtained by measuring a physical quantity relating to a fire to the CPU,
- wherein the CPU is configured to perform an arithmetic processing on the measurement value and transmit a signal based on an arithmetic result,
- wherein the CPU comprises a first memory portion and a second memory portion electrically connected to the first memory portion,
- wherein the first memory portion comprises a first transistor which comprises a first semiconductor,
- wherein the second memory portion comprises a second transistor which comprises a second semiconductor, the second semiconductor having a different band gap width from that of the first semiconductor, and
- wherein the CPU is configured to store data of the first memory portion in the second memory portion before the power gate stops the supply of power, and restore the data of the second memory portion to the first memory portion when the power gate allows to resume the supply of power.
11 more elements
A device comprising:
- a power supply line;
- a power gate electrically connected to the power supply line;
- a CPU electrically connected to the power gate;
- and
- a sensor electrically connected to the CPU,
- wherein the power gate is configured to control supply of power from the power supply line to the CPU,
- wherein the CPU is configured to perform an arithmetic processing on a measurement value received from the sensor and transmit a signal based on a result of the arithmetic processing,
- wherein the CPU comprises a first memory portion and a second memory portion electrically connected to the first memory portion, the second memory portion comprising a transistor, the transistor comprising an oxide semiconductor film which comprises a channel formation region, and
- wherein the CPU is configured to store data of the first memory portion in the second memory portion before the power gate stops the supply of power, and restore the data of the second memory portion to the first memory portion when the power gate allows to resume the supply of power.
6 more elements
Dependencies are inferred from the claim text.