Multi-mode multi-corner clocktree synthesis
AssigneeMentor Graphics Corporation
InventorsSivaprakasam Sunder, Kirk Schollman
Life of this patent
Estimating the term…
Abstract
A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.
Claims24
A method comprising:
- placing, by a computing device, a clock tree in a circuit design, wherein the clock tree is configured to distribute a clock signal to sink pins in the circuit design;
- measuring, by the computing device, multiple clock skew values in the circuit design, wherein each clock skew value is measured with the clock tree having a different respective set of clock tree timing variation parameters;
- and
- performing, by the computing device, an adjustment of the clock tree in the circuit design based, at least in part, on the multiple clock skew values with the clock tree having different respective sets of clock tree timing parameters, wherein the adjustment of the clock tree alters placement of at least one clock tree node in the clock tree.
One or more computer-readable memory devices storing computer-readable instructions that, when executed by one or more processors cause the one or more processors to perform operations comprising:
- placing a clock tree in a circuit design, wherein the clock tree is configured to distribute a clock signal to sink pins in the circuit design;
- measuring multiple clock skew values in the circuit design, wherein each clock skew value is measured with the clock tree having a different respective set of clock tree timing variation parameters;
- and
- adjusting the clock tree for the circuit design based, at least in part, on the multiple clock skew values, wherein the adjustment of the clock tree alters placement of at least one clock tree node in the clock tree.
An apparatus comprising:
- one or more processors;
- and
- one or more tangible memory devices storing processor-readable instructions that, when executed by the one or more processors, cause the one or more processors to place a clock tree in a circuit design to distribute a clock signal to one or more sink pins and measure multiple clock skew values in the circuit design wherein each clock skew value is measured with the clock tree having a different respective set of clock tree timing variation parameters, and wherein the one or more processors, in response to execution of the processor-readable instructions, are further configured to adjust the clock tree for the circuit design based, at least in part, on the multiple clock skew values, wherein the adjustment of the clock tree alters placement of at least one clock tree node in the clock tree.
Dependencies are inferred from the claim text.