Back to results
US 9,310,829 B2Granted
System with feature of saving dynamic power of flip-flop banks
AssigneeFreescale Semiconductor, Inc.
InventorAndrew C. Russell
Life of this patent
Estimating the term…
Abstract
A system comprises a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a gating control module. At a first processor frequency, gating of clock signals is enabled for the first and second plurality of flip-flop circuits. At a second processor frequency, gating of a first of the clock signals is disabled for the first plurality of flip-flop circuits and gating of a second of the clock signals is enabled for the second plurality of flip-flop circuits.
Claims18
A system comprising:
- a first plurality of flip-flop circuits associated with a first threshold frequency above which a setup time requirement for the first plurality of flip-flop circuits is not met;
- a second plurality of flip-flop circuits associated with a second threshold frequency above which a setup time requirement for the second plurality of flip-flop circuits is not met;
- and
- a gating control module operable to:
- enable gating of clock signals for the first and second plurality of flip-flop circuits in response to operation of a processor of the system at a first processor frequency that is below both the first threshold frequency and the second threshold frequency, wherein
- the gating control module is configured to:
- receive an indicator of the first processor frequency,
- compare the indicator of the first processor frequency to an identifier of the first threshold frequency at or below which gating can be enabled for the first plurality of flip-flop circuits, and
- set a first gating enable signal for the first plurality of flip-flop circuits based on whether the identifier of the first threshold frequency is higher than the indicator of the first processor frequency;
- and
- disable gating of a first of the clock signals for the first plurality of flip-flop circuits in response to operation of the processor at a second processor frequency that is above the first threshold frequency and enable gating of a second of the clock signals for the second plurality of flip-flop circuits in response to the second processor frequency being below the second threshold frequency.
8 more elements
A system comprising:
- a first plurality of flip-flop circuits;
- a first frequency associated with the first plurality of flip-flop circuits, wherein the first frequency indicates a first threshold frequency above which a setup time requirement for the first plurality of flip-flop circuits is not met;
- a second plurality of flip-flop circuits;
- a second frequency associated with the second plurality of flip-flop circuits, wherein the second frequency indicates a second threshold frequency above which a setup time requirement for the second plurality of flip-flops is not met;
- a first controller coupled to the first plurality of flip-flop circuits, wherein the first controller is configured to:
- gate a global clock signal to provide a first clock signal to the first plurality of flip-flop circuits when a processing frequency for the system is below the first frequency, and
- a second controller coupled to the second plurality of flip-flop circuits, wherein the second controller is configured to:
- gate the global clock signal to provide a second clock signal to the second plurality of flip-flop circuits when the processing frequency for the system is below the second frequency;
- and
- a gating control module coupled to the first controller and to the second controller, the gating control module configured to:
- compare the processing frequency for the system to the first frequency at or below which gating can be enabled for the first plurality of flip-flop circuits,
- set a first gating enable signal to the first controller based on whether the first frequency is greater than the processing frequency,
- compare the processing frequency for the system to the second frequency at or below which gating can be enabled for the second plurality of flip-flop circuits, and
- set a second gating enable signal to the second controller based on whether the second frequency is greater than the processing frequency.
11 more elements
A method of gating clock signals in a computer processing system comprising:
- receiving a command to change a processor frequency for the processing system, wherein the processing system comprises
- a first set of flip-flop circuits associated with a first identified frequency above which a setup time requirement for the first set of flip-flop circuits is not met, and
- a second set of flip-flop circuits associated with a second identified frequency above which a setup time requirement for the second set of flip-flop circuits is not met;
- determining whether to increase or decrease the processor frequency based on the command;
- and
- when the processor frequency is commanded to decrease,
- transitioning to a lower processor frequency,
- comparing the lower processor frequency to the first identified frequency at or below which gating can be enabled for the first set of flip-flop circuits, and
- generating a first gating enable signal for the first set of flip-flop circuits in response to the lower processor frequency being less than or equal to the first identified frequency, wherein the first gating enable signal controls gating of a first clock signal for the first set of flip-flop circuits.
6 more elements
Dependencies are inferred from the claim text.