Testing SOC with portable scenario models and at different levels

A method comprising:

• receiving a file describing a system-on-a-chip (SoC);
• parsing the file to determine one or more functions to be performed by one or more hardware components of the SoC, wherein the SoC is fabricated on a chip;
• receiving a desired output of the SoC;
• generating a test scenario model based on the desired output of the SoC and the one or more functions to be performed, wherein the test scenario model includes one or more module representations of the functions, wherein the test scenario model further includes one or more connections between two of the module representations, wherein each connection provides a direction of flow of data between the two module representations,
• wherein the desired output acts as a performance constraint for the test scenario model,
• wherein the test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections,
• wherein the test scenario model includes a path from the input via the module representations and the connections to the desired output,
• wherein receiving the file, parsing the file, receiving the desired output, and generating the test scenario model are performed by one or more processors,
• generating a source code test file from the test scenario model and a driver scenario model, the driver scenario model generated based on the desired output of the SoC and one of the functions of the SoC, the driver scenario model including one of the module representations, the one of the module representations having one or more input nodes and one or more output nodes, the desired output of the SoC used to generate an intermediate output within the SoC, the intermediate output used to generate an intermediate input within the SoC based on the one of the functions associated with the one of the module representations;
• compiling the source code test file to generate a compiled file;
• and
• applying the compiled file to a test bench program for testing the SoC, wherein the test bench program is executed by at least one of the one or more processors.

A method comprising:

• receiving a file describing a system-on-a-chip (SoC);
• parsing the file to determine one or more functions to be performed by one or more hardware components of the SoC, wherein the SoC is fabricated on a chip;
• receiving a desired output of the SoC;
• generating a test scenario model based on the desired output of the SoC and the one or more functions to be performed, wherein the test scenario model includes one or more module representations of the functions, wherein the test scenario model further includes one or more connections between two of the module representations, wherein each connection provides a direction of flow of data between the two module representations,
• wherein the desired output acts as a performance constraint for the test scenario model,
• wherein the test scenario model includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections,
• wherein the test scenario model includes a path from the input via the module representations and the connections to the desired output,
• wherein receiving the file, parsing the file, receiving the desired output, and generating the test scenario model are executed by one or more processors,
• generating a source code test file from the test scenario model, an application scenario model, and a driver scenario model, wherein the application scenario model includes at least two of the functions associated with at least two of the module representations, wherein the application scenario model includes the at least two of the module representations and connections between the at least two of the module representations,
• wherein the driver scenario model includes one of the module representations, wherein the one of the module representations of the driver scenario model has one or more input nodes and one or more output nodes, wherein the desired output of the SoC is used to generate an intermediate output of the one of the module representations of the driver scenario model, wherein the intermediate output of the one of the module representations of the driver scenario model is used to generate an intermediate input of the one of the module representations, wherein the intermediate input is generated based on one of the functions associated with the one of the module representations;
• compiling the source code test file to generate a compiled file;
• and
• executing the compiled file by using a test bench program for testing the SoC, wherein the test bench program is executed by at least one of the one or more processors.

A method comprising:

• receiving a file describing a system-on-a-chip (SoC);
• parsing the file to determine one or more functions to be performed by one or more hardware components of the SoC, wherein the SoC is fabricated on a chip;
• receiving a desired output of the SoC;
• generating multiple test scenario models based on the desired output of the SoC and the one or more functions to be performed, wherein each of the test scenario models includes one or more module representations of the functions, wherein each of the test scenario models further includes one or more connections between two of the module representations, wherein each connection provides a direction of flow of data between the two module representations,
• wherein the desired output acts as a performance constraint for each of the test scenario models,
• wherein each of the test scenario models further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections,
• wherein each of the test scenario models includes a path from the input via the module representations and the connections to the desired output,
• wherein receiving the file, parsing the file, receiving the desired output, and generating the test scenario models are executed by one or more processors,
• generating one or more test files for the test scenario models;
• compiling the one or more test files to generate a compiled file;
• providing the test scenario models within the compiled file for execution on a test bench program, wherein the test bench program is executed by at least one of the one or more processors;
• and
• accessing multiple results of execution of the test scenario models from the test bench program for comparison with a plurality of expected outputs,
• wherein accessing the results of execution comprises:
• reading one of the results from a memory location of a memory device coupled to a comparator and to the at least one of the one or more processors that execute the test bench program, wherein the comparator performs the comparison with the expected outputs;
• or
• reading one of the results from a memory queue of one or more memory devices coupled to the comparator and to the at least one of the one or more processors that execute the test bench program;
• or
• reading one of the results from a memory queue of an input/output interface coupled to the comparator and to the at least one of the one or more processors that execute the test bench program;
• or
• reading one of the results from a log file stored within a memory device coupled to the comparator and to the at least one of the one or more processors that execute the test bench program.

A method comprising:

• receiving multiple scenario models, each scenario model providing a path of a direction of execution of one or more intellectual property (IP) blocks associated with a system-on-a-chip (SoC);
• generating one or more test files using the scenario models, the scenario models further including one or more inputs associated with the SoC that are generated based on one or more expected outputs associated with the SoC,
• wherein receiving the multiple scenario models and generating the one or more test files are performed by one or more processors,
• generating one or more events files that include the expected outputs of the scenario models;
• compiling the one or more test files to generate one or more compiled files;
• executing a test bench program to execute the one or more compiled files to execute the IP blocks along the paths of the one or more scenario models to further generate one or more test outputs, wherein the test bench program is executed by at least one of the one or more processors;
• comparing the test outputs with the expected outputs to determine whether the SoC passed a test;
• and
• back propagating one of the expected outputs via one of the scenario models to generate a stimulus, wherein executing the test bench program includes applying the stimulus to the one of the scenario models to generate one of the test outputs, wherein the one or more inputs includes the stimulus.

A method comprising:

• receiving multiple scenario models, wherein each of the scenario models provides a path of a direction of execution of one or more intellectual property (IP) blocks associated with a system-on-a-chip (SoC);
• generating one or more test files using the scenario models;
• generating one or more events files, wherein each event file includes an expected output associated with one of the scenario models, wherein each event file further includes an arbitrary operation that is not within the test files,
• wherein each test file includes a condition for execution of the arbitrary operation;
• compiling the one or more test files to generate a compiled file;
• determining whether the condition is satisfied by executing the compiled file using a test bench program, wherein the test bench program is executed by one or more processors;
• and
• performing the one of the arbitrary operations upon determining that the condition is satisfied,
• wherein the method is executed by at least one of the one or more processors.

A method comprising:

• receiving a test scenario model based on a desired output of a system-on-a chip (SoC) and one or more functions to be performed by one or more hardware components of the SoC, wherein the SoC is fabricated on a chip, wherein the test scenario model includes one or more module representations of the functions, wherein the test scenario model further includes one or more connections between two of the module representations, wherein each connection provides a direction of flow of data between the two of the module representations,
• wherein the desired output acts as a performance constraint for the test scenario model,
• wherein the test scenario model further includes an input for providing to the SoC, wherein the input is generated based on the desired output, the module representations, and the one or more connections,
• wherein the test scenario model includes a path from the input via the module representations and the connections to the desired output;
• generating a source code test file including the test scenario model, an application scenario model, and a driver scenario model, wherein the application scenario model includes at least two of the functions associated with at least two of the module representations, wherein the application scenario model includes at least two of the module representations and connections between the at least two of the module representations,
• wherein the driver scenario model includes one of the module representations, wherein the one of the module representations of the driver scenario model has one or more input nodes and one or more output nodes, wherein the desired output of the SoC is used to generate an intermediate output of the one of the module representations of the driver scenario model, wherein the intermediate output of the one of the module representations of the driver scenario model is used to generate an intermediate input of the one of the module representations, wherein the intermediate input generated is based on one of the functions associated with the one of the module representations;
• compiling the source code test file to generate a compiled file;
• executing the compiled file using a test bench program for testing the SoC, wherein the test bench program is executed by a processor;
• generating an events file,
• wherein the events file includes a first expected output for the test scenario model, a second expected output for the application scenario model, and a third expected output for the driver scenario model,
• wherein the test bench program is executed to generate multiple results of execution of the compiled file, wherein a first one of the results is associated with a first event identifier identifying the first expected output and is generated by execution of the test scenario model within the test bench program, wherein a second one of the results is associated with a second event identifier identifying the second expected output and is generated by execution of the application scenario model within the test bench program, wherein a third one of the results is associated with a third event identifier identifying the third expected output and generated by execution of the driver scenario model within the test bench program;
• receiving the first event identifier, the second event identifier, and the third event identifier from the test bench program during execution of the test bench program;
• and
• comparing the first result with the first expected output, the second result with the second expected output, and the third result with the third expected output upon receiving the first event identifier, the second event identifier, and the third event identifier, wherein comparing the first result with the first expected output, the second result with the second expected output, and the third result with the third expected output is performed to determine whether the SoC passed a test.

A method comprising:

• receiving a test scenario model based on a desired output of a system-on-a chip (SoC) and one or more functions to be performed by one or more hardware components of the SoC, wherein the SoC is fabricated on a chip, wherein the test scenario model includes one or more module representations of the functions, wherein the test scenario model further includes one or more connections between two of the module representations, wherein each connection provides a direction of flow of data between the two of the module representations,
• wherein the desired output acts as a performance constraint for the test scenario model,
• the test scenario model further including an input for providing to the SoC, wherein the input is generated based on the desired output, the module representations, and the one or more connections,
• wherein the test scenario model includes a path from the input via the module representations and the connections to the desired output,
• generating a source code test file from the test scenario model and an application scenario model, wherein the application scenario model includes at least two of the module representations and one or more connections between the at least two module representations, wherein the application scenario model includes at least two of the functions associated with at least two of the module representations;
• compiling the source code test file to generate a compiled file;
• executing the compiled file using a test bench program for testing the SoC, wherein the test bench program is executed by a processor;
• generating an events file,
• wherein the events file includes a first expected output for the test scenario model and a second expected output for the application scenario model,
• wherein the test bench program is executed to generate multiple results of execution of the compiled file, wherein a first one of the results is associated with a first event identifier identifying the first expected output and is generated by execution of the test scenario model within the test bench program, wherein a second one of the results is associated with a second event identifier identifying the second expected output and is generated by execution of the application scenario model within the test bench program;
• receiving the first event identifier and the second event identifier during execution of the test bench program;
• and
• comparing the first result with the first expected output and the second result with the second expected output upon receiving the first event identifier and the second event identifier, wherein comparing the first result with the first expected output and the second result with the second expected output is performed to determine whether the SoC passed a test.