US 9,310,431 B2 · Diagnosis framework to shorten yield learning cycles of advanced processes

Abstract

The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

Claims20

Dependent claims

A method to locate and diagnose defects in an integrated circuit, comprising:

designing a plurality of DUT structures within a defect under test (DUT) carrier unit, wherein a respective DUT structure comprises at least one process sensitive component;
designing a test structure by arranging the plurality of DUT structures within the DUT carrier unit, wherein a respective DUT structure forms a connection between an output of a first logic device and an input of a second logic device;
simulating an expected output for a defect within the test structure, and storing the expected output in a look-up table (LUT);
applying heuristic yield analysis to the test structure to identify the defect within the test structure;
and
utilizing the LUT to locate the defect without performing physical yield analysis (PFA).

3 more elements

A tool arrangement configured to locate and diagnose defects in an integrated circuit, comprising:

a test vector generator configured to define a test vector corresponding to a test structure;
a fault simulation tool configured to receive the test vector from the test vector generator and to simulate an expected output of applying the test vector to the test structure which corresponds to a failure location within the test structure;
a look-up table (LUT) configured to receive the expected output from the fault simulation tool and to store the expected output;
and
a measurement and analysis tool configured to receive a measured output of applying the test vector to the test structure, and to compare the measured output to the expected output to determine the failure location within the test structure without performing physical failure analysis (PFA).

2 more elements

Dependencies are inferred from the claim text.

Diagnosis framework to shorten yield learning cycles of advanced processes

Life of this patent

Diagnosis framework to shorten yield learning cycles of advanced processes

Life of this patent

Abstract

Claims20