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US 9,310,430 B2Granted
Semiconductor integrated circuit and test control method thereof
AssigneeHynix Semiconductor Inc.
InventorHong-Sok Choi
Life of this patent
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Abstract
A semiconductor integrated circuit includes a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals, a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, wherein the transmission circuit outputs the test mode group signals with maintaining a previous output, when the test decoding signals different from each other are sequentially activated, and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals.
Claims17
A semiconductor integrated circuit comprising:
- a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals;
- a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, such that when the test decoding signals different from each other are sequentially activated, the transmission circuit outputs a corresponding newly-activated test mode group signal while maintaining an activation state of a previously-activated test mode group signal;
- and
- a test mode signal output circuit configured to output a plurality of test mode signals corresponding to a plurality of test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals,
- wherein test modes belonging to different test mode groups are concurrently entered due to the corresponding newly-activated test mode group signal being output and the activation state of the previously-activated test mode group signal being maintained, and any test modes belonging to a same test mode group are selectively reset.
2 more elements
A test control method of a semiconductor integrated circuit, comprising:
- activating a first test mode group signal among a plurality of test mode group signals for a first test mode group including a plurality of first test modes;
- latching the first test mode group signal;
- activating a first test mode signal for entering one or more of the first test modes, in response to a plurality of test mode select signals and the first test mode group signal latched in the latching of the first test mode group signal;
- activating a second test mode group signal among the plurality of test mode group signals for a second test mode group including a plurality of second test modes;
- latching the second test mode group signal;
- and
- activating a second test mode signal for entering one or more of the second test modes, in response to the plurality of test mode select signals and the second test mode group signal latched in the latching of the second test mode group signal,
- wherein, in the activating of the second test mode group signal, the latching of the second test mode group signal, and the activating of the second test mode signal, the first test mode signal is maintained to be activated,
- wherein when the first test mode group signal and the second test mode signal different from each other are sequentially activated, the test mode group signals are outputted to maintain a previous output,
- wherein the test modes belonging to different test mode groups of the first and second test mode groups are concurrently entered, and any test modes belonging to a same test mode group of the first test mode or the second test mode are selectively reset.
7 more elements
A test control method of a semiconductor integrated circuit, comprising:
- activating a first test mode group signal of a first period among a plurality of test mode group signals for a first test mode group including a plurality of test modes;
- first latching the first test mode group signal;
- activating a first test mode signal for entering one of the test modes, in response to a plurality of test mode select signals and the first test mode group signal latched in the first latching of the activating the first test mode group signal;
- activating the first test mode group signal of a second period;
- deactivating the first test mode signal in response to the first test mode group signal of the second period, and second latching the first test mode group signal of the second period;
- and
- activating a second test mode signal for entering another of the test modes, in response to the test mode select signals and the first test mode group signal latched in the second latching,
- wherein when the first test mode group signal and the second test mode signal different from each other are sequentially activated, a corresponding newly-activated second test mode group signal is output while an activation state of a previously-activated first test mode group signal is maintained,
- wherein the test modes belonging to different test mode groups of the first and second test mode groups are concurrently entered due to the corresponding newly-activated second test mode group signal being output and the activation state of the previously-activated first test mode group signal being maintained, and any test modes belonging to a same test mode group of the first test mode or the second test mode are selectively reset.
6 more elements
Dependencies are inferred from the claim text.