On-going reliability monitoring of integrated circuit chips in the field

An integrated circuit chip comprising:

• a functional block comprising a first memory array comprising first bitlines;
• a test block comprising a second memory array comprising second bitlines, the first memory array and the second memory array being a same type memory array;
• a monitor tracking environmental conditions associated with said test block;
• and
• an embedded processor in communication with said test block and said monitor,
• said embedded processor selectively alternating operation of said test block between a stress mode and a test mode during functioning of said integrated circuit chip within a product,
• said embedded processor performing said selectively alternating of said operation of said test block between said stress mode and said test mode when said integrated circuit chip is powered-on within said product,
• said first bitlines being pre-charged at a nominal operating voltage during said operation of said test block in said stress mode and said test mode,
• said embedded processor causing said second bit lines to be pre-charged at a higher voltage level than said nominal operating voltage during said stress mode,
• said embedded processor causing said second bitlines to be pre-charged at a same voltage level as said nominal operating voltage and to be subjected to testing during said test mode, and
• said embedded processor further being remote access service (RAS) enabled so as to allow results of said testing and said tracking be reported out during said functioning of said integrated circuit chip.

An integrated circuit chip comprising:

• a functional block comprising a first static random access memory (SRAM) array comprising first static random access memory (SRAM) cells and first bitlines;
• a test block comprising a second static random access memory (SRAM) array comprising second static random access memory (SRAM) cells and second bitlines;
• and
• an embedded processor selectively alternating operation of said test block between a stress mode and a test mode during functioning of said integrated circuit chip within a product,
• said first bitlines being pre-charged to a nominal operating voltage during memory operations are performed by said functional block and regardless of whether said operation of said test block is in said stress mode or said test mode,
• said embedded processor performing said selectively alternating of said operation of said test block between said stress mode and said test mode when said integrated circuit chip is powered-on within said product,
• said embedded processor causing said first static random access memory (SRAM) cells and said second static random access memory (SRAM) array to be exercised at a same frequency during said stress mode,
• said embedded processor causing said second bitlines to be pre-charged at a higher voltage level than said nominal operating voltage of said first bitlines during said stress mode,
• said embedded processor causing said second bitlines to be pre-charged to a same voltage level as said nominal operating voltage of said first bitlines and to be subjected to testing during said test mode;
• and
• said embedded processor further being remote access service (RAS) enabled so as to allow results of said testing to be reported out during said functioning of said integrated circuit chip.