Reliability assessment of capacitor device

A method of testing, comprising:

• providing a plurality wafer-level devices having a metal-oxide-metal (MOM) capacitor formed thereon;
• performing a process control monitor (PCM) test, wherein the PCM test includes:
• determining a threshold leakage level for each of the MOM capacitors;
• providing an initial voltage to each of the MOM capacitors wherein the initial voltage is provided while the MOM capacitors are at approximately 125 C;
• measuring a first leakage level from each of the MOM capacitors while providing the initial voltage;
• increasing a voltage provided to each of the MOM capacitors from the initial voltage to a failure voltage;
• measuring a second leakage level from at least one of the MOM capacitors when the failure voltage is applied, wherein the failure voltage is breakdown of the oxide of the MOM capacitor;
• comparing the failure voltage in volts to a time dependent dielectric breakdown (TDDB) test result in a unit of time;
• and
• determining a first TDDB lifetime for the plurality of wafer-level devices using the compared failure voltage and TDDB test result.

A method of testing a semiconductor device, comprising:

• providing a wafer-level device including a metal-oxide-metal (MOM) capacitor disposed on a first semiconductor substrate;
• forcing a voltage through the MOM capacitor while the MOM capacitor is at a temperature greater than room temperature;
• and
• ramping the voltage forced through the MOM capacitor from the initial voltage to a failure voltage, wherein the failure voltage is greater than the initial voltage and is determined by a leakage failure of the MOM capacitor, wherein the ramping the voltage is performed at approximately 125 C;
• correlating the failure voltage to a time dependent dielectric breakdown (TDDB) lifetime to determine a TDDB lifetime associated with the wafer-level device using a graph of breakdown voltage test results in volts (V) on a first axis and lifetime on a second axis, wherein the breakdown voltage test results are obtained from testing a plurality of wafer-level devices and the lifetime is obtained from testing a plurality of product-level devices;
• and
• dispositioning devices disposed on a second semiconductor substrate based on the failure voltage and the TDDB lifetime.