An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.
Drawings
Claims22
An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent, wherein said capping layer includes at least one input/output port above at least one cavity, said input/output port for introducing fluid into, and removing fluid from, said cavity;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure;
and
wiring connecting the gates and the 2D lattice structures externally.
4 more elements
An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities, wherein said 2D lattice structure is selected from a carbon nanotube film, graphene, transition metal dichalcogenides and black phosphorus;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure;
and
wiring connecting the gates and the 2D lattice structures externally.
4 more elements
An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
one or more structural features in said at least one cavity, said one or more structural features modifying fluid flow through said at least one cavity;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure;
a dielectric layer covering said 2D lattice structure;
contacts through said dielectric layer to said 2D lattice structure, said wiring connecting to said 2D lattice structure through said contacts;
and
wiring connecting the gates and the 2D lattice structures externally.
7 more elements
An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure;
and
wiring connecting the gates and the 2D lattice structures externally, wherein said gates and contact to said gates are transparent conductors, selected from Indium Tin Oxide (ITO) or a 2D lattice material.
4 more elements
An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure;
and
wiring connecting the gates and the 2D lattice structures externally, wherein at one or more cavity, said gate is one of a pair of gates separated from said cavity by the same said 2D lattice structure.
30 Sep 2034Estimated · howhide20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.
#The present invention generally relates to analyzing liquid flow and liquid-solid interface interaction and more particularly to an integrated device for self-contained liquid flow and liquid-solid interface interaction analysis that enables the comparison with and the validation of computational models of such liquid solid interactions.
#The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
#FIG. 1 shows an example of fabricating a lab-on-a-chip for simulating fluid flow according to a preferred embodiment of the present invention;
#FIG. 2A shows an example of a plan view of a simple lab-on-a-chip site;
Detailed description2,969 words
#Turning now to the drawings and, more particularly, FIG. 1 shows an example 100 of fabricating a lab-on-a-chip for simulating fluid flow according to a preferred embodiment of the present invention. Essentially, the lab-on-a-chip fabrication 100 uses typical state of the art semiconductor integrated circuit fabrication techniques (e.g., CMOS chip fabrication) to form a template or templates and sufficient wiring and analysis support circuitry. The template has physical patterns that represent fluid flow in a geological space. Once formed and verified/validated, the template simulates fluid flow through fluid channels representative of the geological space. Typically the fully formed template structure is capped with a capping layer. The capping layer may include the simulation support circuitry, or the simulation support circuitry may be opposite the cap, on or in, the same semiconductor wafer supporting the template(s). Thus, the lab-on-a-chip enables liquid flow analysis through a defined space with defined properties, and experimental validation of the results on a wide range (orders of magnitude) of scale lengths under well-defined laboratory conditions, ranging from nanometers (nm) to millimeters (mm).
#Fabrication begins 102 with physical information that determines the boundary system conditions. Next, transforming 104 the physical information algorithmically, equations mathematically describe the physical structures. A template file 106, created from the equations, is input to both flow simulation 108 and template manufacturing 110. Flow simulation 108 predicts the flow behavior in the geometric structure defined by the template file 106. Simultaneously, template preprocessing determines 110 specific manufacturing requirements, and provided manufacturing is feasible within manufacturing process, the template file 106 is converted 112 into a suitable format for manufacturing a physical template 114. If the template file 106 is unmanufacturable, the template file 106 may be adjusted or recreated. Comparing 116 flow simulation 108 results against the physical template 114, either the comparison results do not match and the template file 106 requires additional tweaking; or the physical template 114 is complete. If additional tweaking is necessary, then additional physical information 102 may be required to iteratively arrive at a suitable template file 106. The completed physical template has use 118, for example, modeling oil reservoir flow or in bio-engineering.
#The physical information 102 is geometrical data describing physical patterns and includes boundary conditions defining a flow field within a porous media. The boundary conditions may be extracted from the field experimentally, or physically measured, e.g., computerized tomography (CT) scanning rock samples.