US 9,306,509 B2 · Receiver having a wide common mode input range

Abstract

In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

Claims20

Dependent claims

A differential amplifier, comprising:

first and second input terminals;
a first differential pair of transistors having a first conductivity type and gates coupled to the first and second input terminals, respectively;
a second differential pair of transistors having a second conductivity type and gates coupled to the first and second input terminals, respectively;
a first pair of adjustable current sources coupled to the first differential pair of transistors and configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal;
a second pair of adjustable current sources coupled to the second differential pair of transistors and configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal;
and
a third pair of adjustable current sources coupled to the second differential pair of transistors and configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

4 more elements

An analog front-end circuit, comprising:

a first electrostatic discharge circuit having inputs for receiving a differential signal from a transmission medium;
termination resistors coupled to differential outputs of the first electrostatic discharge circuit and configured to match the impedance of the analog front end to impedance of the transmission medium;
an equalizer circuit including a first differential amplifier circuit coupled to receive the differential signal from differential outputs of the termination resistors, the first differential amplifier circuit including:
an NMOS differential pair having inputs connected to the differential outputs of the termination resistors, the NMOS differential pair and configured to receive and amplify the differential signal using a high common mode voltage, the NMOS differential pair biased during operation by a first pair of adjustable current sources in response to a first bias current control signal;
a PMOS differential pair having inputs connected to the differential outputs of the termination resistors, the PMOS differential pair configured to receive and amplify the differential signal using a low common mode voltage, the PMOS differential pair biased during operation by a second pair of adjustable current sources in response to the first bias current control signal and by a third pair of adjustable current sources in response to a second bias current control signal;
and
a control circuit configured to:
when operating in a low common mode, enable operation of the PMOS differential pair and disable operation of the NMOS differential pair;
and
when operating in a high common mode, enable operation of the NMOS differential pair and disable operation of the PMOS differential pair.

7 more elements

A method of amplifying a differential signal, comprising:

providing the differential signal to inputs of a PMOS differential pair;
providing the differential signal to inputs of an NMOS differential pair;
in response to a common mode control signal indicating a high common mode:
enabling the NMOS differential pair by biasing the NMOS differential pair with a first pair of adjustable current sources in response to a first bias current control signal;
and
disabling the PMOS differential pair;
and
in response to the common mode control signal indicating a low common mode:
enabling the PMOS differential pair by biasing the PMOS differential pair with a second pair of adjustable current sources in response to the first bias current control signal and biasing the PMOS differential pair with a third pair of adjustable current sources in response to a second bias current control signal;
and
disabling the NMOS differential pair.

8 more elements

Dependencies are inferred from the claim text.

Receiver having a wide common mode input range

Life of this patent

Receiver having a wide common mode input range

Life of this patent

Abstract

Claims20