Hetero junction field effect transistor and method for manufacturing the same

A hetero junction field effect transistor comprising:

• a first compound semiconductor layer on a substrate, the first compound semiconductor layer having a V shape recess region on an upper portion of the first compound semiconductor layer;
• a second compound semiconductor layer on the first compound semiconductor layer;
• a gate insulating layer on the second compound semiconductor layer;
• and
• a gate electrode on the gate insulating layer,
• wherein the gate insulating layer includes a first portion in the V shape recess region and having a V shape, a second portion on the second compound semiconductor layer and having a horizontal line shape, and a third portion between the first and second portions and extending in a direction perpendicular to a top surface of the substrate;
• wherein the gate insulating layer is in contact with the first compound semiconductor layer;
• wherein a 2-dimensional electron gas (2DEG) region is provided in an upper portion of the first compound semiconductor layer in a state where a voltage is not applied to the gate electrode;
• and
• wherein the 2DEG region is not provided under a contacting portion of the gate insulating layer and the first compound semiconductor layer.