System and method for dictionary-based cache-line level code compression for on-chip memories using gradual bit removal
AssigneeQUALCOMM Incorporated
InventorsAmin Ansari, Vito Bica, Richard Senior
Life of this patent
Estimating the term…
Loading patent…
AssigneeQUALCOMM Incorporated
InventorsAmin Ansari, Vito Bica, Richard Senior
Estimating the term…
A multi-pass compression iteratively removes combinations of bits from locations in each word of a cache line of an uncompressed data stream. For each combination of removed bits, the remaining bits in the word values of the cache line are analyzed to generate a compression score. A highest compression score triggers the building of a dictionary from the remaining bits in the word values of the cache line. After a dictionary is built, the method may continue iteratively to create subsequent dictionaries from the words that remain uncompressed in the cache line. To decompress a word, a first bit section of the compressed word is used to identify a dictionary that is then queried for bits indexed in a second bit section of the compressed word. The uncompressed word is reconstructed by interleaving the queried bits with the removed combination of bits from a third bit section of the word.
A method for cache-line level compression and decompression (“CLADE”) of a data stream in a system on a chip (“SoC”) in a portable computing device (“PCD”), the method comprising:
A system for cache-line level compression and decompression (“CLADE”) of a data stream in a system on a chip (“SoC”) in a portable computing device (“PCD”), the system comprising:
A computer program product comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for cache-line level compression and decompression (“CLADE”) of a data stream in a system on a chip (“SoC”) in a portable computing device (“PCD”), said method comprising:
Dependencies are inferred from the claim text.