Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programming

A memory controller, comprising:

• a storage device comprising a set of instructions, the set of instructions comprising:
• instructions for programming one or more data memory cells in a set of data memory cells, the set of data memory cells are eligible to store data, the set of data memory cells is in a plurality of NAND strings, each NAND string of the plurality of NAND string comprising a first dummy memory cell which is a non-data-storing memory cell and is provided between memory cells of the set of data memory cells which are in the NAND string and a select gate transistor of the NAND string;
• instructions for setting a first control gate voltage for the first dummy memory cells during the programming of the one or more data memory cells in the set of data memory cells;
• instructions for performing read operations involving the set of data memory cells, including applying at least one demarcation voltage to selected memory cells in the set of data memory cells while applying a pass voltage to unselected memory cells in the set;
• instructions for determining a first count of the first dummy memory cells which have a threshold voltage above an upper checkpoint voltage, after the read operations;
• and
• instructions for setting a second control gate voltage, higher than the first control gate voltage, for the first dummy memory cells during a subsequent programming operation involving one or more data memory cells in the set of data memory cells, if the first count exceeds a threshold;
• and
• a processor operable to execute the set of instructions.

A method for operating a memory device, comprising:

• performing a first plurality of program-erase cycles involving a set of data memory cells, the set of data memory cells is in a plurality of NAND strings, each NAND string of the plurality of NAND string comprising a first dummy memory cell which is a non-data-storing memory cell and is provided between memory cells of the set of data memory cells which are in the NAND string and a select gate transistor of the NAND string, wherein each program-erase cycle of the first plurality of program-erase cycles comprises a program operation and an erase operation;
• setting a first control gate voltage for the first dummy memory cells during program voltages of program operations of the first plurality of program-erase cycles;
• after the first plurality of program-erase cycles, performing a first evaluation of threshold voltages of the first dummy memory cells, the performing the first evaluation comprises determining a first count of the first dummy memory cells which have a threshold voltage above a first upper checkpoint voltage and determining whether or not the first count exceeds a threshold;
• and
• if the first count exceeds the threshold, setting a second control gate voltage, higher than the first control gate voltage, for the first dummy memory cells during program voltages of program operations of a second plurality of program-erase cycles which are after the first plurality of program-erase cycles.