Write operations in spin transfer torque memory
AssigneeIntel Corporation
InventorsHelia Naeimi, Shih-Lien L. Lu, Charles Augustine
Life of this patent
Estimating the term…
Abstract
In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.
Claims25
A controller comprising logic to:
- identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;
- mask write operations to the second plurality of cells in the row;
- set the first plurality of cells to a parallel state;
- mask write operations to the first plurality of cells in the row;
- and
- set the second plurality of cells to an anti-parallel state.
A memory, comprising:
- at least one spin-transfer torque (STT) memory device;
- and
- a controller comprising logic to:
- identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;
- mask write operations to the second plurality of cells in the row;
- set the first plurality of cells to a parallel state;
- mask write operations to the first plurality of cells in the row;
- and
- set the second plurality of cells to an anti-parallel state.
An electronic device comprising:
- a processor;
- at least one spin-transfer torque (STT) memory device;
- and
- a controller comprising logic to:
- identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;
- mask write operations to the second plurality of cells in the row;
- set the first plurality of cells to a parallel state;
- mask write operations to the first plurality of cells in the row;
- and
- set the second plurality of cells to an anti-parallel state.
A computer program product comprising logic instructions stored in a non-transitory computer-readable medium which, when executed by a controller, configure the controller to:
- identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;
- mask write operations to the second plurality of cells in the row;
- set the first plurality of cells to a parallel state;
- mask write operations to the first plurality of cells in the row;
- and
- set the second plurality of cells to an anti-parallel state.
Dependencies are inferred from the claim text.