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US 9,294,132 B1Granted
Dual-stage data decoding for non-volatile memories
AssigneeProton Digital Systems, Inc.
InventorsBorja Peleato-Inarrea, Andrei Vityaev, Nenad Miladinovic
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Abstract
A method and system for decoding information read from a non-volatile memory uses a two stage decoding algorithm, where the first stage is a high-speed, low precision decoder and the second stage is a low-speed, high precision decoder. Most of the time only the first stage of the decoder is used, which lowers the average power consumption of the decoding process.
Claims15
A memory system with error correction, the system comprising:
- a flash memory organized into blocks and having a controller that keeps track of Program/Erase (P/E) cycles for each block of the flash memory;
- a read/write channel encoder/decoder storing error correction code data;
- a read channel decoder comprising of two decoders, high-speed low-precision decoder and low-speed high-precision decoder,
- wherein the high-speed low-precision decoder is used for low P/E cycles, and the low-speed high-precision decoder is used for high P/E cycles on a block-by-block basis,
- wherein the high-speed low-precision decoder is an LDPC (Low Density Parity Check) erasure decoder that uses two input symbols and three symbols for internal calculations, and
- wherein received values from the read/write channel are converted to Log-Likelihood-Ratios (LLR) using lookup tables and based on a number of P/E cycles and based on result of previous reads.
3 more elements
A memory system with error correction, the system comprising:
- a flash memory having row and columns and organized into a plurality of pages, with multiple pages organized into blocks;
- a controller that keeps track of Program/Erase (P/E) cycles for each block and provides stored data bits for each memory cell and a representation of cell voltage used to produce each of the stored data bits;
- a read/write channel encoder/decoder storing error correction code data, the read/write channel encoder/decoder including (a) a high-speed low-precision decoder used for error correction when the cell voltage is not substantially different from a programmed voltage of the memory cell, and (b) a low-speed high-precision decoder used for error correction when the cell voltage is substantially different from the programmed voltage of the memory cell,
- wherein the high-speed low-precision decoder or the low-speed high-precision decoder is used on a block-by-block basis,
- wherein the high-speed low-precision decoder is an LDPC (Low Density Parity Check) erasure decoder that uses two input symbols and three symbols for internal calculations, and
- wherein received values from the read/write channel are converted to Log-Likelihood-Ratios (LLR) using lookup tables and based on a number of P/E cycles and based on result of previous reads.
3 more elements
Dependencies are inferred from the claim text.