Configurable quad byte framer

A method for generating a framer suitable for interfacing between one or more data converters and a logic device, the method comprising:

• receiving hardware instance parameters including a total number of bits per converter, a number of lane(s), and a size of an input bus for providing one or more samples from the one or more data converters;
• synthesizing to hardware a transport layer circuit according to the hardware instance parameters, wherein the transport layer circuit maps the one or more samples from the one or more data converters into one or more frames in a frame memory;
• and
• synthesizing to hardware a data link layer circuit according to the hardware instance parameters, wherein the data link layer circuit provides the one or more frames over one or more lanes to a logic device according to a serialized interface;
• wherein the transport layer circuit maps the one or more samples and the data link layer circuit provides the one or more frames according to an active specification defined by:
• a number of data converter(s), a number of sample(s) per converter, the total number of bits per converter, the number of lane(s), and a frame size.

One or more non-transitory tangible media that includes code for execution and when executed by a processor is operable to perform operations to provide a framer, the operations comprising:

• receiving hardware instance parameters, the hardware instance parameters including:
• a total number of bits per converter, a number of lane(s), and a size of an input bus for providing one or more samples from the one or more data converters;
• and
• synthesizing hardware to include:
• a transport layer circuit according to the hardware instance parameters, wherein the transport layer circuit maps one or more samples from the one or more data converters into one or more frames in a frame memory;
• and
• a data link layer circuit according to the hardware instance parameters, wherein the data link layer circuit provides the one or more frames over one or more lanes to a logic device according to a serialized interface;
• wherein the transport layer circuit maps the one or more samples and the data link layer circuit provides the one or more frames according to an active specification defined by:
• a number of data converter(s), a number of sample(s) per converter, the total number of bits per converter, the number of lane(s), and a frame size.