Data receiver circuit and method of adaptively controlling equalization coefficients using the same

A data receiver circuit comprising:

• n over-sampling circuits configured to receive n respective clock signals and an input signal, generate n respective sampling signals, and latch n respective equalizing signals generated in response to the n respective sampling signals and a decision feedback equalizer (DFE) control signal to output n respective pre-recovery signals, the n over-sampling circuits configured to receive as feedback the n respective pre-recovery signals, n being a natural number equal to or greater than 2;
• a data recovery circuit configured to receive the n clock signals and the n pre-recovery signals and output a recovered input signal, a lowest data transition detection signal, and a highest data transition detection signal;
• and
• a DFE adaptation control circuit configured to generate the DFE control signal in a first mode using the highest data transition detection signal, and further generate the DFE control signal in a second mode using the lowest data transition detection signal,
• wherein the lowest data transition detection signal indicates an Xth interval of one clock cycle, the Xth interval corresponding to an interval determined to have a lowest number of transitions of the input signal, and
• wherein the highest data transition detection signal indicates a Yth interval of one clock cycle, the Yth interval corresponding to an interval determined to have a highest number of transitions of the input signal.

A receiver circuit comprising:

• n sampling receivers configured to sample an input signal and output n respective sampling signals in response to n respective clock signals each having n intervals within a clock cycle, n being a natural number equal to or greater than 2;
• n decision feedback equalizer (DFE) circuits configured to equalize the n respective sampling signals in response to a DFE control signal and generate n respective pre-recovery signals in response to the n equalized sampling signals and n respective previous pre-recovery signals, the DFE control signal for changing an equalization ability of the n DFE circuits;
• and
• a data recovery circuit configured to select one of the n respective pre-recovery signals, and output the selected n pre-recovery signal as a recovered input signal,
• wherein the data recovery circuit is further configured to generate n transition detection signals each indicating at least one of the n intervals and the number of transitions of the input signal at the at least one of the n intervals, and output a highest data transition detection signal and a lowest data transition detection signal based on the n transition detection signals,
• wherein the lowest data transition detection signal indicates an Xth interval of one clock cycle, the Xth interval corresponding to an interval determined to have a lowest number of transitions of the input signal, and
• wherein the highest data transition detection signal indicates a Yth interval of one clock cycle, the Yth interval corresponding to an interval determined to have a highest number of transitions of the input signal.