Apparatuses, methods, and systems for jitter equalization and phase error detection

A circuit comprising:

• a first input terminal to receive a first input signal;
• a second input terminal to receive a second input signal;
• and
• a phase error detector coupled to the first and second input terminals, the phase error detector to:
• perform an XOR operation between the first and second input signals to generate an xor signal;
• and
• determine a phase error between the first and second input signals based on a mark/space ratio of the xor signal by being configured to:
• perform a logic AND operation between the xor signal and a clock signal to generate a first count signal;
• perform a logic AND operation between an xorb signal and the clock signal to generate a second count signal, the xorb signal being an inverted version of the xor signal;
• and
• determine the phase error between the first and second input signal based on a difference between a first number of transitions in the first count signal and a second number of transitions in the second count signal over a same time period.

A system, comprising:

• a touchscreen display;
• a processor coupled to the touchscreen display;
• a power supply to provide a supply voltage;
• and
• a communication circuit coupled to the processor and to the power supply, the communication circuit including:
• a supply modulator to modulate the supply voltage at a modulation frequency during a training process of the communication circuit;
• a data path to pass a data signal, the data path including one or more circuit blocks to process the data signal;
• a clock path to pass a clock signal, the clock path including one or more circuit blocks to process the clock signal;
• a jitter equalizer coupled with the data path or the clock path to provide a delay to the respective data signal or clock signal;
• an error detector to measure a phase error between the data signal and the clock signal;
• and
• a training controller to, while the supply voltage is modulated at the modulation frequency, adjust the delay provided by the jitter equalizer based on the measured phase error.

A method, comprising:

• performing a logic XOR operation between first and second input signals to generate an xor signal;
• performing a logic AND operation between the xor signal and a clock signal to generate a first count signal;
• performing a logic AND operation between an xorb signal and the clock signal to generate a second count signal, the xorb signal being an inverted version of the xor signal;
• counting a number of rising edges in the first count signal for a time period to obtain a first counter value;
• counting a number of rising edges in the second count signal for a time period to obtain a second counter value;
• and
• determining a phase error between the first and second input signals based on the first and second counter values.