US 9,287,899 B1 · Forward error correction

Abstract

Methods and circuits are disclosed for forward-error-correction (FEC) decoding. A plurality of symbols are received in an interleaved format of rows and columns of the symbols. A plurality of FEC decoding iterations are performed on the plurality of symbols. Each decoding iteration performs FEC decoding of the rows of the plurality of symbols and performs FEC decoding of the columns of the plurality of symbols. After performing the decoding iterations, rows in error and columns in error of the plurality of symbols are determined. In response to the determined rows in error and the determined columns in error matching a deadlock pattern, symbols at intersections of the determined rows and columns in error are determined. Bits of one or more symbols of the determined symbols are inverted. After the inverting of the bits, one or more of the FEC decoding iterations are performed.

Claims20

Dependent claims

A method for forward error correction (FEC) decoding, comprising:

receiving a plurality of symbols in an interleaved format of rows and columns of the symbols;
performing a plurality of FEC decoding iterations on the plurality of symbols, each decoding iteration including:
performing FEC decoding of the rows of the plurality of symbols;
and
performing FEC decoding of the columns of the plurality of symbols;
after performing the FEC decoding iterations, determining rows in error of the plurality of symbols and columns in error of the plurality of symbols;
and
in response to the determined rows in error and the determined columns in error matching a deadlock pattern of a set of deadlock patterns:
determining symbols of the plurality of symbols at intersections of the determined rows in error and the determined columns in error;
and
inverting bits of one or more symbols of the determined symbols;
and
performing one or more of the FEC decoding iterations after the inverting of the bits.

10 more elements

A circuit for forward error correction (FEC) decoding, comprising:

a first FEC decoder configured and arranged to:
receive a first set of symbols in an interleaved format having rows of the first set of symbols interleaved with columns of the first set of symbols;
and
perform a plurality of FEC decoding iterations on the first set of symbols to produce a second set of symbols, each decoding iteration including FEC decoding of the rows of the first set of symbols and FEC decoding of the columns of the first set of symbols;
and
a deadlock recovery circuit coupled to the first FEC decoder and configured to:
determine rows and columns of symbols in error in the second set of symbols;
and
in response to the determined rows and columns of symbols in error matching a deadlock pattern, invert bits of one or more symbols of the second set of symbols at intersection points of the determined rows and columns of symbols in error to produce a third set of symbols;
and
a second FEC decoder coupled to the deadlock recovery circuit and configured and arranged to perform one or more of the FEC decoding iterations on the third set of symbols.

8 more elements

Dependencies are inferred from the claim text.

Forward error correction

Life of this patent

Forward error correction

Life of this patent

Abstract

Claims20