US 9,287,891 B1 · Successive approximation register analog to digital converters

Abstract

A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Claims16

Dependent claims

A successive approximation register (SAR) analog to digital converter (ADC) circuit receiving an analog input signal and operating in a sample phase and a conversion phase following the sample phase to generate a digital output signal, comprising:

a plurality of capacitors, coupled to a summing node, wherein before the conversion phase, a target capacitor among the plurality of capacitors is coupled to a direct current (DC) voltage and the other capacitors among the plurality of capacitors are coupled to the analog input signal;
a comparator having an input terminal coupled to the summing node, wherein in the conversion phase, the comparator performs a comparison operation to a summing voltage at the summing node;
and
a logic unit having a plurality of weighting values corresponding to the plurality of capacitors respectively and generating the digital output signal according to the weighting values and a comparison result of the comparison operation,
wherein the DC voltage has a first voltage level or a second voltage level different from the first voltage level according to a random sequence, and
wherein the weighting value of the target capacitor is calibrated according to the digital output signal and the random sequence.

3 more elements

a first switch coupled between a first voltage and a summing node;
a plurality of capacitors each having a first terminal coupled to the summing node and further having a second terminal;
a plurality of second switches, wherein each second switch is coupled between the second terminal of one of the plurality of capacitors and a second voltage;
a plurality of switch circuits receiving the analog input signal, wherein each switch circuits is coupled to the second terminal of one of the plurality of capacitors and, before the conversion phase, provides a DC voltage or the analog input signal to the corresponding capacitor;
a comparator having an input terminal coupled to the summing node, wherein in the conversion phase, the comparator performs a comparison operation to a summing voltage at the summing node;
a logic unit having a plurality of weighting values corresponding to the plurality of capacitors respectively and generating the digital output signal according to the weighting values and a comparison result of the comparison operation;
and
an extraction and compensation unit receiving the digital output signal,
wherein when a target capacitor among the plurality of switch circuits receive the DC voltage from the corresponding switch circuit, the DC voltage has a first voltage level or a second voltage level different from the first voltage level based on a random sequence, and
wherein the extraction and compensation unit obtains a calibrated weighting value according to the digital output signal and the random sequence, and the calibrated weighting value serves as the weighting value of the target capacitor.

7 more elements

Dependencies are inferred from the claim text.

Successive approximation register analog to digital converters

Life of this patent

Successive approximation register analog to digital converters

Life of this patent

Abstract

Claims16