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US 9,287,889 B2Granted
System and method for dynamic path-mismatch equalization in time-interleaved ADC
AssigneeBoard of Regents, The University of Texas System
InventorsYun Chiu, Benwei Xu
Life of this patent
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Abstract
Disclosed are methods and systems implementing digital background calibration techniques for identifying and remedying dynamic path-mismatch errors in time-interleaved analog-to-digital converters (TI-ADC). The disclosed systems and methods employ a calibration technique specifically focuses on removing the timing skew and input bandwidth mismatches by equalizing each sub-ADC in an array to a common reference ADC using direct input derivative information. The errors are identified by correlating the ensuing conversion error to the input derivatives of various orders to identify the mismatch parameters. Simple passive high-pass filters (HPF) are used to extract input derivatives followed by one-bit quantizers.
Claims26
A method for calibrating a time-interleaved analog-to-digital converter (TI-ADC), comprising:
- sampling a common input signal, said sampling performed by an interleaved array of sub-analog-to-digital converters (ADCs), said sampling corresponding to a clock signal associated with said TI-ADC;
- converting, via each sub-ADC, the input signal into a digital output signal;
- sampling, via a reference ADC, the input signal, said reference ADC sampling aligning with said sub-ADC sampling;
- converting, via the reference ADC, the input signal into a digital output signal;
- determining mismatch errors between the reference ADC output signal and each sub-ADC output signal, said determination comprising simultaneously identifying a timing skew mismatch and an input bandwidth mismatch between the output signals of the sub-ADCs and reference ADC, wherein
- said identification of the timing skew mismatch comprises using timing skew estimation circuitry,
- said identification of the input bandwidth mismatch comprises using input bandwidth estimation circuitry, and
- said timing skew estimation circuitry and said input bandwidth estimation circuitry are utilized simultaneously to simultaneously identify said timing skew mismatch and said input bandwidth mismatch;
- and
- generating correction signals in accordance with the determined mismatch errors, said correction signals accounting for said timing skew mismatch and said input bandwidth mismatch.
7 more elements
A device comprising:
- a processing unit for processing an output of a time-interleaved analog-to-digital converter (TI-ADC), said TI-ADC configured to calibrate an input signal into said output for said processing unit, said TI-ADC comprising:
- a plurality of sub-ADCs, each of said plurality of sub-ADCs sampling said input signal at specific time points specified by a corresponding sampling clock to generate a subset of digital output signals;
- a reference ADC, said reference ADC sampling said input signal at said specific time points to generate a reference digital output signal;
- a first order high-pass filter, said first order high-pass filter extracting input derivatives from said input signal, said input derivatives associated with a skew equalization of a time skew error;
- a second order high-pass filter, said second order high-pass filter extracting second derivatives from said input signal, said second derivatives associated with bandwidth equalization of a bandwidth mismatch;
- and
- a comparator, said comparator minimizing channel-to-channel mismatch error caused by simultaneous skew equalization and bandwidth equalization, said minimizing enabling correction of signals to each sub-ADC.
4 more elements
A time-interleaved analog-to-digital converter (ADC) comprising:
- a plurality of interleaved sub-ADCs configured to sample a common input signal, said sampling corresponding to a clock signal associated with said TI-ADC, each sub-ADC further configured to convert the input signal into a digital output signal;
- a reference ADC configured to sample the input signal, said reference ADC sampling aligning with said sub-ADC sampling, the reference ADC further configured to convert the input signal into a digital output signal;
- and
- a calibration unit configured to determine mismatch errors between the reference ADC output signal and each sub-ADC output signal, the calibration unit further configured to simultaneously identify (a) a timing skew mismatch utilizing timing skew estimation circuitry and (b) an input bandwidth mismatch utilizing input bandwidth estimation circuitry between each output signal, said calibration unit further configured to generate correction signals in accordance with the determined mismatch errors, said correction signals accounting for said timing skew and said input bandwidth mismatch, wherein the correction signals are fed back to each sub-ADC.
1 more element
A time-interleaved analog-to-digital converter (ADC) comprising:
- a plurality of interleaved sub-ADCs configured to sample a common input signal, said sampling corresponding to a clock signal associated with said TI-ADC, each sub-ADC further configured to convert the input signal into a digital output signal;
- a reference ADC configured to sample the input signal, said reference ADC sampling aligning with said sub-ADC sampling, the reference ADC further configured to convert the input signal into a digital output signal;
- and
- a calibration unit configured to determine mismatch errors between the reference ADC output signal and each sub-ADC output signal, wherein
- the calibration unit further configured to identify a timing skew mismatch utilizing timing skew estimation circuitry between each output signal,
- the timing skew estimation circuitry comprises an analog derivative filter to obtain an input signal derivative, and
- said calibration unit further configured to generate correction signals in accordance with the determined mismatch errors, said correction signals accounting for said timing skew mismatch, wherein the correction signals are fed back to each sub-ADC.
4 more elements
Dependencies are inferred from the claim text.