Dynamic reference frequency for fractional-N Phase-Locked Loop

A circuit comprising:

• a Phase-Locked Loop (PLL) configured to supply a local oscillator signal to a mixer of a transceiver;
• a Programmable Comparison Reference Clock Signal Generator (PCRCSG) configured to supply a comparison reference clock signal to the PLL, wherein the comparison reference clock signal has a first frequency;
• and
• a lookup circuit configured to supply PLL control information to the PCRCSG based on transmit channel information;
• wherein the transceiver is configured to transmit a transmit signal according to the transmit channel information,
• wherein the PCRCSG is configured to change the first frequency of the comparison reference clock signal to a second frequency based on the PLL control information;
• wherein the transmit channel information comprises a jammer frequency being within a predetermined frequency value of a receive channel frequency of the transceiver, a jammer signal strength being above a predetermined level, and a carrier signal to noise ratio being below a predetermined threshold;
• wherein the PCRCSG is configured to return the comparison reference clock signal to the first frequency, after the transceiver has operated for a time period using the comparison reference clock signal at the second frequency, in response to a determination that the jammer signal strength has not been reduced in magnitude.

A circuit comprising:

• a jammer detection circuit configured to generate an interrupt signal in response to detecting a jammer and further configured to output at least one value indicating a frequency of the detected jammer is within a predetermined frequency value of a receive channel frequency, a strength of the detected jammer is above a predetermined level, and a carrier signal to noise ratio is below a predetermined threshold;
• a lookup circuit configured to generate phase-locked loop control information responsive to the at least one value;
• and
• a Phase-Locked Loop (PLL) of a local oscillator of a receiver, the PLL being configured to change a clock signal from a first frequency to a second frequency based on the phase-locked loop control information;
• wherein the PLL is configured to return the clock signal to the first frequency, after the PLL has operated the clock signal for a time period at the second frequency, in response to a determination that the strength of the detected jammer has not been reduced in magnitude.

A computer program product, comprising:

• a computer-readable tangible medium comprising instructions executable by a processor to cause the processor to:
• execute an interrupt service routine responsive to receiving an interrupt, wherein the interrupt service routine includes reading at least one value stored in a register, the at least one value indicating a frequency of a detected jammer is within a predetermined frequency value of a receive channel frequency, a strength of a detected jammer is above a predetermined level, and a carrier signal to noise ratio is below a predetermined threshold;
• and
• change a frequency of a comparison reference clock signal to be provided to a phase-locked loop (PLL), wherein the frequency is changed from a first frequency to a second frequency based on the at least one value;
• wherein the instructions are executable by the processor to cause the processor to return the comparison reference clock signal to the first frequency, after operating the comparison reference clock signal for a time period at the second frequency, in response to a determination that detected jammer signal strength has not been reduced in magnitude.

An apparatus comprising:

• means for transmitting a transmit signal;
• means for generating a local oscillation signal based on a comparison reference clock signal;
• means for detecting a jammer associated with the transmit signal;
• and
• means for changing a frequency of the comparison reference clock signal from a first frequency to a second frequency based on a jammer frequency being within a predetermined frequency value of a receive channel frequency of the means for transmitting, a jammer signal strength being above a predetermined level, and a carrier signal to noise ratio being below a predetermined threshold;
• wherein the means for changing the frequency is configured to return the comparison reference clock signal to the first frequency, after the means for transmitting has operated for a time period using the comparison reference clock signal at the second frequency, in response to a determination that the jammer signal strength has not been reduced in magnitude.

A mobile device comprising:

• a phase locked loop (PLL) coupled to generate a local oscillation signal based on a comparison reference clock signal;
• a jammer detection circuit coupled to generate a signal in response to detecting a jammer having a jammer frequency within a predetermined frequency value of a receive channel frequency and a jammer signal strength above a predetermined level, and a carrier signal to noise ratio being below a predetermined threshold;
• and
• a processor responsive to the signal to select at least one value of a lookup table of values, the processor determining whether the PLL operates according to a fractional mode corresponding to a first frequency or according to an integer mode corresponding to a second frequency and further changing a frequency of the comparison reference clock signal from the first frequency to the second frequency based on the at least one value;
• wherein the processor is configured to return the comparison reference clock signal to the first frequency, after operating the comparison reference clock signal for a time period at the second frequency, in response to a determination that detected jammer signal strength has not been reduced in magnitude.