All digital phase locked loop with configurable multiplier having a selectable bit size

A method performed by an all digital phase locked loop, the method comprising:

• generating a digital code using a time-to-digital converter based on a phase difference between a reference clock signal and a variable clock signal;
• selecting, using the time-to-digital converter, a bit size of a configurable multiplier, the bit size being selected based on a determined minimum number of bits to obtain a reciprocal of a variable clock period, the minimum number of bits being based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient;
• and
• multiplying, using the time-to-digital converter, the digital code by the reciprocal of the variable clock period to output a fractional error correction value.

An all digital phase locked loop, comprising:

• a time-to-digital converter configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal;
• a configurable multiplier coupled with the time-to-digital converter, the configurable multiplier having a selectable bit size, the selectable bit size being based on a determined minimum number of bits to obtain a reciprocal of a variable clock period, the minimum number of bits being based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient;
• a reference phase accumulator configured to compute an accumulation of a frequency control word of the reference clock signal, the frequency control word being a ratio of an expected variable clock frequency to the reference clock signal;
• and
• a phase detector configured to output a phase error based, at least in part, on a fractional error correction value and the accumulation of the frequency control word,
• wherein the time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output the fractional error correction value.