Multi-lane re-timer circuit and multi-lane reception system

A multi-lane re-timer circuit comprising:

• a clock generation circuit configured to generate a base clock;
• and
• a plurality of reception circuits configured to generate a reception clock based on the base clock and receive input data signals from a plurality of lanes according to the reception clock,
• wherein each of the plurality of the reception circuits includes:
• a phase frequency detector configured to detect a phase difference and a frequency difference between the input data signal and the reception clock, and generate a phase difference signal and a frequency difference signal;
• a clock data regeneration controller configured to generate a control signal based on the phase difference signal;
• a phase rotator configured to generate the reception clock from the base clock according to the control signal;
• and
• a decision circuit configured to receive the input data signal according to the reception clock, and
• wherein the clock generation circuit includes:
• an input selector configured to receive a first selection signal and a second selection signal, select, based on the first selection signal and the second selection signal, as a signal to be used all of pieces of the frequency difference signal output by phase frequency detectors of the plurality of the reception circuits and select, based on the second selection signal, as the signal to be used a part of the pieces of the frequency difference signal;
• a charge pump configured to generate a charge signal according to a selection result selected by the input selector;
• a loop filter configured to remove a high frequency component from the charge signal to output a voltage control signal;
• and
• a voltage controlled oscillator configured to generate the base clock according to the voltage control signal.