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US 9,287,879 B2Granted
Semiconductor device having features to prevent reverse engineering
AssigneeVerisiti, Inc.
InventorWilliam Eli Thacker
Life of this patent
Estimating the term…
Abstract
It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
Claims4
An electronic circuit comprising:
- a plurality of logic devices implementing logic functions, wherein at least one logic device implementing a logic function comprises an invisible bias generator having a first floating gate device having a first geometry and a first bias voltage, and a second floating gate device having a second geometry and a second bias voltage, wherein the first geometry and the second geometry are the same and the second bias voltage is different than the first bias voltage,
- wherein the first floating gate device includes a first doping level of a diffusion area and the second floating gate device includes a second doping level of a diffusion area, and wherein the first doping level is different than the second doping level.
Dependencies are inferred from the claim text.