US 9,287,872 B2 · PVT compensation scheme for output buffers

Abstract

In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.

Claims14

Dependent claims

A method for calibrating buffers in an integrated circuit, the method comprising:

(a) applying a selected source-current level to a first pull-down buffer at a first node;
(b) adjusting drive-strength level of the first pull-down buffer until a first voltage at the first node reaches a first reference voltage level to determine a N-type calibration setting for the first pull-down buffer;
(c) applying the N-type calibration setting to a second pull-down buffer connected to a first pull-up buffer at a second node;
and
(d) adjusting drive-strength level of the first pull-up buffer until a second voltage at the second node reaches a second reference voltage level to determine a P-type calibration setting for the first pull-up buffer.

2 more elements

An integrated circuit comprising:

pull-down calibration circuitry comprising:
a first pull-down buffer;
a programmable current source connected to apply a selected source-current level to the first pull-down buffer at a first node;
a first voltage reference source configured to generate a first reference voltage;
a first differential comparator configured to compare a first voltage at the first node to the first reference voltage;
and
a first controller configured to adjust drive-strength level of the first pull-down buffer until the first voltage at the first node reaches the first reference voltage level to determine an N-type calibration setting for the first pull-down buffer;
and
pull-up calibration circuitry comprising:
a second pull-down buffer to which the N-type calibration setting is applied;
a first pull-up buffer connected to the second pull-down buffer at a second node;
a second voltage reference source configured to generate a second reference voltage;
a second differential comparator configured to compare a second voltage at the second node to the second reference voltage;
and
a second controller configured to adjust drive-strength level of the first pull-up buffer until the second voltage at the second node reaches the second reference voltage level to determine a P-type calibration setting for the first pull-up buffer.

12 more elements

Dependencies are inferred from the claim text.

PVT compensation scheme for output buffers

Life of this patent

PVT compensation scheme for output buffers

Life of this patent

Abstract

Claims14