Data bus synchronizer without an enable signal input
AssigneeTexas Instruments Incorporated
InventorGopalkrishna Ullal Nayak
Life of this patent
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Abstract
A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal. The data bus synchronizer further includes a logic block configured to generate the load enable signal on satisfaction of a logic condition.
Claims14
A data bus synchronizer comprising:
- a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, wherein the plurality of registers receive a value on the asynchronous bus and wherein the asynchronous bus is synchronized to a control clock input such that a latest stable value on the asynchronous bus is always sampled, irrespective of a toggling rate of the asynchronous bus with respect to the control clock input, thereby generating the synchronized output;
- a last register of the plurality of registers, configured to generate the synchronized output in response to a load enable signal;
- and
- a logic block that is configured to generate the load enable signal on satisfaction of a logic condition.
A phase locked loop comprising:
- a phase locked loop controller configured to generate a clock divider value on an asynchronous bus;
- a divider controller receiving the clock divider value and a control clock input, configured to generate a division value, wherein the divider controller comprises a data bus synchronizer;
- wherein the data bus synchronizer further comprises:
- a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, wherein the plurality of registers receive a value on the asynchronous bus and wherein the asynchronous bus is synchronized to a control clock input such that a latest stable value on the asynchronous bus is always sampled, irrespective of a toppling rate of the asynchronous bus with respect to the control clock input, thereby generating the synchronized output;
- a last register of the plurality of registers, configured to generate the synchronized output in response to a load enable signal;
- and
- a logic block that is configured to generate the load enable signal on satisfaction of a logic condition;
- and
- a divider configured to generate a clock output in response to the division value and a phase locked loop clock input.
A method of generating a synchronized output from an asynchronous bus input, comprising:
- applying a value on an asynchronous bus to a plurality of registers arranged in a cascade;
- sampling the asynchronous bus directly without an enable signal wherein sampling includes sampling a latest stable value on the asynchronous bus irrespective of a toggling rate of the asynchronous bus with respect to a control clock input;
- and sampling every value on the asynchronous bus when the toggling rate of the asynchronous bus is one third the toggling rate of the control clock input;
- generating a load enable signal on satisfaction of a logic condition;
- and
- configuring a last register of the plurality of registers to generate the synchronized output in response to the load enable signal.
Dependencies are inferred from the claim text.