Logic cell for programmable logic device

A method performed by a logic cell within a programmable logic device, the method comprising:

• selecting between a first output signal from a first logic element and a second output signal from a second logic element based on a select signal from a routing network to produce a combinatorial logic signal;
• selecting between the combinatorial logic signal and the select signal from the routing network to produce a register data input signal;
• receiving the register data input signal with a register;
• and
• receiving a SET signal and a RESET signal from the routing network with the register, wherein the logic cell is one of a plurality of logic cells in a super logic cell in the programmable logic device and the SET signal and the RESET signal from the routing network are received by registers in each of the plurality of logic cells in the super logic cell.

A programmable logic device, comprising:

• a routing network;
• a plurality of super logic cells coupled to the routing network, each of the plurality of super logic cells comprises a plurality of logic cells, wherein each logic cell in the plurality of logic cells receives at least one common signal from the routing network and wherein each logic cell comprises a plurality of input terminals coupled to receive different signals from the routing network and at least one output terminal and comprises:
• a first logic element having a first plurality of input terminals coupled to the routing network and a first output terminal;
• a second logic element having a second plurality of input terminals coupled to the routing network and a second output terminal;
• a first multiplexor having a first mux input terminal coupled to the first output terminal and a second mux input terminal coupled to the second output terminal and a first multiplexor select terminal coupled to receive a dynamic select signal from the routing network, the first multiplexor having a third output terminal;
• a second multiplexor having a third mux input terminal directly coupled to the third output terminal and a fourth mux input terminal coupled to the first multiplexor select terminal coupled to receive the dynamic select signal from the routing network, the second multiplexor having a fourth output terminal;
• and
• a register having a register data terminal coupled to the fourth output terminal and a fifth output terminal coupled to an output terminal of the logic cell.

A programmable logic device comprising a logic cell, the logic cell comprising:

• a register having a register data terminal, a clock terminal, and a first output terminal;
• a first multiplexor comprising a first input terminal, a second input terminal coupled to the first output terminal of the register, a select terminal, and a second output terminal coupled to an output terminal of the logic cell;
• and
• a logic gate having a third input terminal coupled to the select terminal of the first multiplexor, a fourth input terminal coupled to receive a clock signal, and a third output terminal, wherein the third output terminal of the logic gate is coupled to the clock terminal of the register.

A method performed by a logic cell in a programmable logic device, the method comprising:

• receiving a signal with a register;
• selecting an output signal to be produced by the logic cell from one of an output signal from the register or a second signal from within the logic cell;
• and
• gating a clock signal to the register, wherein the clock signal is provided to the register when the output signal from the register is selected as the output signal and the clock signal is gated off when the second signal from within the logic cell is selected as the output signal.