Flexible input/output transceiver
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
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Abstract
An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit. The pre-driver circuit can modify a data signal in response to the feedback control signal and the data signal. A driver circuit is coupled to the pre-driver circuit and can provide a driver output signal responsive to the modified data signal. A receiver can be coupled to the driver to receive the driver output signal. The receiver includes a level shifting circuit that shifts the received signal to a voltage level determined by a selected signaling interface.
Claims29
A driver comprising:
- a feedback circuit configured to provide a feedback control signal responsive to a mode select signal, a data output signal, and a driver output signal;
- a pre-driver circuit configured to receive the data output signal and the feedback control signal, and to modify the data output signal responsive to the feedback control signal;
- and
- a driver circuit configured to provide the driver output signal responsive to the modified data output signal.
A memory device comprising:
- a memory array;
- a plurality of vertical connectors;
- and
- a plurality of I/O transceivers coupled between the memory array and the plurality of vertical connectors, each transceiver of the plurality of I/O transceivers coupled to a different one of the plurality of vertical connectors;
- wherein each of the plurality of I/O transceivers comprises:
- a feedback circuit configured to provide a feedback control signal responsive to a mode select signal, a data output signal, and a driver output signal;
- a pre-driver circuit configured to receive the data output signal and the feedback control signal, and to modify the data output signal responsive to the feedback control signal;
- and
- a driver circuit configured to provide the driver output signal responsive to the modified data output signal.
A system comprising:
- a controller;
- and
- a memory device coupled to the controller, the memory device comprising:
- a plurality of stacked memory dies coupled over a plurality of vertical connectors;
- and
- a logic die coupled with the plurality of stacked memory dies;
- wherein each memory die of the plurality of stacked memory dies comprises a respective plurality of I/O transceivers coupled to the plurality of vertical connectors, each I/O transceiver of the plurality of I/O transceivers comprising:
- a feedback circuit configured to provide a feedback control signal responsive to a mode select signal, a data output signal, and a driver output signal;
- a pre-driver circuit configured to receive the data output signal and the feedback control signal, and to modify the data output signal responsive to the feedback control signal;
- and
- a driver circuit configured to provide the driver output signal responsive to the modified data output signal.
A method for communicating in a memory device, the method comprising:
- receiving a mode select signal at a feedback circuit;
- receiving a serial data signal at the feedback circuit;
- providing a feedback control signal from the feedback circuit to a pre-driver circuit responsive to an output signal of a driver circuit, the serial data signal, and the mode select signal;
- providing a modified serial data signal from the pre-driver to the driver circuit responsive to the serial data signal and the feedback control signal;
- and
- providing the output signal from the driver circuit responsive to the modified serial data signal.
A memory device comprising:
- a stack of memory dies, wherein each of the memory dies of the stack of memory dies comprises a respective memory array;
- and
- a logic die coupled with the stack of memory dies,
- wherein each of the memory dies of the stack of memory dies comprises a respective plurality of I/O transceivers, coupled between the respective memory array and a plurality of vertical connectors, and configured to selectively implement one of a plurality of signaling interfaces.
Dependencies are inferred from the claim text.