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US 9,287,858 B1Granted
Low leakage shadow latch-based multi-threshold CMOS sequential circuit
AssigneeTexas Instruments Incorporated
InventorVipul Kumar Singhal
Life of this patent
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Abstract
Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.
Claims20
A multi-threshold CMOS sequential circuit, comprising:
- a first latch circuit formed of transistors having threshold voltages in a first range and powered from a switchable voltage node to provide a primary data path storing at least one data bit during active mode operation of the sequential circuit;
- and
- a second latch circuit, comprising:
- inverters formed of transistors selectively powered from a continuous voltage node and having threshold voltages in a second range higher than the first range, the inverters of the second latch circuit selectively operative for low-power retention mode operation of the sequential circuit to latch the at least one data bit transferred from the first latch circuit,
- a transfer gate formed of transistors having threshold voltages in the second range and providing a data transfer path between the first and second latch circuits during transitions from active to low-power retention mode and vice versa, the transmission gate operative to disconnect the first and second latch circuits from one another during both active mode and low-power retention mode operation of the sequential circuit, and
- a second switching circuit selectively operative to disconnect the inverters of the second latch circuit from the continuous voltage node during active mode operation of the sequential circuit.
3 more elements
An integrated circuit, comprising:
- a first switching circuit including a power switching transistor selectively operative to decouple a switchable voltage node from a continuous voltage node or to decouple the first latch circuit from a ground node when a switching control signal is in a first state for low-power retention mode operation of the sequential circuit, and to couple the switchable voltage node to the continuous voltage node or to couple the first latch circuit with the ground node when the switching control signal is in a second state for active mode operation of the sequential circuit, the power switching transistor having a threshold voltage in the second range;
- a sequential circuit, comprising:
- a first latch circuit formed of transistors having threshold voltages in a first range and powered from a switchable voltage node to provide a primary data path storing at least one data bit during active mode operation of the sequential circuit, and
- a second latch circuit, comprising:
- inverters formed of transistors selectively powered from the continuous voltage node and having threshold voltages in a second range higher than the first range, the inverters of the second latch circuit selectively operative in low-power retention mode operation of the sequential circuit to latch the at least one data bit transferred from the first latch circuit,
- a transfer gate formed of transistors having threshold voltages in the second range and providing a data transfer path between the first and second latch circuits during transitions from active to low-power retention mode and vice versa, the transmission gate operative to disconnect the first and second latch circuits from one another during both active mode and low-power retention mode operation of the sequential circuit, and
- a second switching circuit formed of transistors having threshold voltages in the first range, the second switching circuit selectively operative to disconnect the inverters of the second latch circuit from the continuous voltage node during active mode operation of the sequential circuit;
- and
- a control circuit selectively operative in a first mode to provide the switching control signal in the first state for low-power retention mode operation of the sequential circuit, the control circuit selectively operative in a second mode to provide the switching control signal in the second state for active mode operation of the sequential circuit.
6 more elements
Dependencies are inferred from the claim text.