Tracking circuit

A method comprising:

• utilizing a switching circuit having a first terminal, a second terminal, and a third terminal, the first terminal being a control terminal;
• causing, by a tracking circuit coupled with the first terminal and the second terminal, the first terminal to have a first voltage value of the first terminal sufficient to turn on the switching circuit if the second terminal is at a first voltage value of the second terminal;
• and
• causing, by the tracking circuit, the first terminal to have a second voltage value of the first terminal sufficient to turn off the switching circuit if the second terminal is at a second voltage value of the second terminal,
• wherein
• the third terminal has a voltage value greater than the first voltage value of the first terminal;
• the first voltage value of the second terminal is less than the voltage value of the third terminal;
• and
• the second voltage value of the second terminal is greater than the voltage value of the third terminal.

A circuit comprising:

• a first PMOS transistor having a first P drain, a first P source, and a first P gate;
• a second PMOS transistor having a second P drain, a second P source, and a second P gate;
• a third PMOS transistor having a third P drain, a third P source, and a third P gate;
• a first NMOS transistor having a first N drain, a first N source, and a first N gate;
• a second NMOS transistor having a second N drain, a second N source, and a second N gate;
• and
• a third NMOS transistor having a third N drain, a third N source, and a third N gate,
• wherein
• the first P source is coupled to the second P gate and configured to receive a first voltage;
• the second P source is coupled to the first P gate and the third N source at a first node;
• the first P drain is coupled to the second P drain and the third N gate at an output node;
• the third N drain is configured to receive a first voltage value;
• the first N drain is coupled to the second N gate and configured to receive the first voltage;
• the second N drain is coupled to the first N gate and the third P drain at a second node;
• the first N source is coupled to the second N source and the third P gate;
• the third P source is configured to receive a second voltage value;
• the first node is electrically connected to the second node;
• the second voltage value is less than the first voltage value;
• and
• the first voltage is configured to switch between a third voltage value less than the second voltage value and a fourth voltage value greater than the third voltage value.

A circuit comprising:

• a first latching circuit configured to receive a first voltage and a second voltage having a second voltage value and generate an output voltage having an output voltage value at an output node, the first voltage having a first reference voltage value and a second reference voltage value;
• and
• a second latching circuit coupled to the first latching circuit at a common node and configured to receive the first voltage and a third voltage having a third voltage value,
• wherein
• the first latching circuit is configured to have the output voltage at the third voltage value of the third voltage or to have the output voltage at the second reference voltage value of the first voltage;
• and
• the third voltage value is less than the second voltage value.