Semiconductor device and semiconductor system including the same
AssigneeSK hynix Inc.
InventorKie-Bong Ku
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal.
Claims12
A semiconductor device comprising:
- a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal;
- a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal;
- and
- an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal.
A semiconductor system comprising:
- a memory device suitable for latching data in response to a data strobe signal that is outputted from a controller;
- and
- a controller suitable for retransmitting the data in response to a reset signal that is generated by the memory device,
- wherein the memory device comprises:
- a pipe latch suitable for sequentially latching and outputting data in response to pipe input/output control signals;
- a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to the reset signal;
- and
- an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the reset signal.
Dependencies are inferred from the claim text.