Signal conversion circuit, PLL circuit, delay adjustment circuit, and phase control circuit
AssigneeAika Design Inc.
InventorsToru Nakura, Kunihiro Asada
Life of this patent
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Abstract
A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
Claims10
A signal conversion circuit for generating a signal according to an inputted pulse signal while receiving pulse width of the pulse signal,
- wherein the signal conversion circuit takes samples from the pulse signal, converts the pulse signal into binary digital output values comprising two values based on signal values taken as the samples, converts the pulse signal into an analog intermediate output value which is between the two values based on signal values taken as the samples only when the digital output values are changing between the two values, and generates a converted signal having the digital output values and the intermediate output value.
A phase control circuit comprising:
- a PLL circuit that compares phase of an input signal and phase of an output signal from an oscillation circuit to detect phase difference and generates an intended oscillation signal by controlling the oscillation circuit based on the phase difference;
- and
- a delay adjustment circuit that compares phase of the input signal and phase of a delayed output signal obtained via a pulse width controlled delay circuit to detect phase difference and generates an intended phase adjusted signal by controlling, at the pulse width controlled delay circuit and based on the phase difference, delay of the oscillation signal outputted from the PLL circuit,
- wherein the pulse width controlled delay circuit includes:
- a signal conversion circuit that takes samples from a pulse signal generated based on phase difference between the input signal and the delayed output signal, converts the pulse signal into binary digital output values comprising two values based on signal values taken as the samples, converts the pulse signal into an analog intermediate output value which is between the two values based on signal values taken as the samples only when the digital output values are changing between the two values, and generates a converted signal having the digital output values and the intermediate output value;
- and
- a control circuit that generates the phase adjusted signal by delaying the oscillation signal according to the converted signal.
Dependencies are inferred from the claim text.