Systems and methods for 100 percent duty cycle in switching regulators

A method comprising:

• receiving an input voltage on an input terminal of a first switching transistor of a buck switching regulator, the first switching transistor having an output terminal coupled to an output node through an inductor;
• generating a ramp signal having a period;
• and
• comparing the ramp signal and an error signal to produce a modulation signal,
• wherein in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increases above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for a period of time greater than one or more full periods of the ramp signal, and wherein the first switching transistor remains turned on when the error signal is greater than a maximum value of the ramp signal, wherein a current through the inductor to the output node increases continuously across multiple periods of the ramp signal when the error signal is above the maximum value of the ramp signal.

A buck switching regulator circuit comprising:

• a first switching transistor having an input terminal to receive an input voltage and an output terminal coupled to an output node through an inductor;
• means for generating a ramp signal, the ramp signal having a period;
• and
• means for comparing the ramp signal and an error signal to produce a modulation signal,
• wherein in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increases above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for a period of time greater than one or more full periods of the ramp signal, and wherein the first switching transistor remains turned on when the error signal is greater than a maximum value of the ramp signal, wherein a current through the inductor to the output node increases continuously across multiple periods of the ramp signal when the error signal is above the maximum value of the ramp signal.