Voltage regulators with improved startup, shutdown, and transient behavior

A soft-start/soft-stop (SS) controller for a voltage regulator comprising:

• a power up/down detector configured to perform at least one selected from a group consisting of:
• detecting a power on condition of the voltage regulator to determine a start-up time period;
• and
• detecting a power off condition of the voltage regulator to determine a shut-down time period;
• a variable on-resistance (Ron) controller configured to generate a Ron control signal to control a variable Ron of a MOS power switching device in the voltage regulator, wherein the MOS power switching device comprises a plurality of MOS switches;
• and
• a ramped reference voltage signal generator configured to perform at least one selected from a group consisting of:
• increasing a voltage level of a ramped reference voltage signal using a pre-determined ramp-up rate during the start-up time period;
• and
• decreasing the voltage level of the ramped reference voltage signal using a pre-determined ramp-down rate during the shut-down time period,
• wherein the ramped reference voltage signal is supplied to the voltage regulator for controlling an output voltage level of the voltage regulator,
• wherein the Ron control signal is configured to:
• turn on each of the plurality of MOS switches in a first sequential order during the start-up time period of the voltage regular;
• and
• turn off each of the plurality of MOS switches in a second sequential order during the shut-down time period of the voltage regulator,
• wherein the variable Ron control signal turns on each of the plurality of MOS switches synchronously with respect to the incrementing of the n-bit count value, and
• wherein the variable Ron control signal turns off each of the plurality of MOS switches synchronously with respect to the decrementing of the n-bit count value.

A method to reduce output overshoots and undershoots in a voltage regulator, comprising:

• incrementing, based on a clock signal, an n-bit count value starting from a pre-determined minimum value and ending at a pre-determined maximum value, wherein the incrementing is initiated in response to detecting a power on condition of the voltage regulator;
• decrementing, based on the clock signal, the n-bit count value starting from the pre-determined maximum value and ending at the pre-determined minimum value, wherein the decrementing is initiated in response to detecting a power off condition of the voltage regulator;
• generating a voltage ramp that:
• increases in proportion to the n-bit count value when the n-bit count value increments;
• and
• decreases in proportion to the n-bit count value when the n-bit count value decrements;
• generating an up/down ramped reference voltage signal by selecting a time-dependent minimum of the voltage ramp and a DC reference voltage, wherein the up/down ramped reference voltage signal follows the voltage ramp incrementing until clipping at the DC reference voltage and follows the voltage ramp decrementing until clipping at a minimum voltage;
• and
• supplying the up/down ramped reference as a reference voltage to the voltage regulator for controlling an output voltage level of the voltage regulator.