Superstrate sub-cell voltage-matched multijunction solar cells
AssigneeAlliance for Sustainable Energy, LLC
InventorsAngelo Mascarenhas, Kirstin Alberi
Life of this patent
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Abstract
Voltage-matched thin film multijunction solar cell and methods of producing cells having upper CdTe pn junction layers formed on a transparent substrate which in the completed device is operatively positioned in a superstate configuration. The solar cell also includes a lower pn junction formed independently of the CdTe pn junction and an insulating layer between CdTe and lower pn junctions. The voltage-matched thin film multijunction solar cells further include a parallel connection between the CdTe pn junction and lower pn junctions to form a two-terminal photonic device. Methods of fabricating devices from independently produced upper CdTe junction layers and lower junction layers are also disclosed.
Claims19
A voltage-matched multijunction solar cell comprising:
- a CdTe pn junction layer comprising a CdTe upper sub-cell;
- a lower pn junction layer comprising a lower sub-cell;
- a transparent insulating layer positioned between the CdTe pn junction layer and the lower pn junction layer;
- a transparent superstrate positioned opposite the CdTe pn junction layer from the transparent insulating layer;
- and
- an interdigitated p-type and n-type back contact comprising Si and associated with the lower sub-cell on the side of the lower sub-cell opposite the transparent insulating layer,
- wherein the CdTe upper sub-cell and the lower sub-cell are voltage-matched and are connected to each other in parallel.
A method of fabricating a voltage-matched multijunction solar cell, the method comprising:
- forming a CdTe upper sub-cell within a CdTe pn junction layer on a transparent substrate;
- forming a lower sub-cell within a lower pn junction layer;
- providing a transparent insulating layer between the CdTe pn junction layer and the lower pn junction layer;
- forming an interdigitated p-type and n-type back contact comprising Si and associated with the lower sub-cell on the side of the lower sub-cell opposite the transparent insulating layer;
- subsequently joining the CdTe pn junction layer and the lower pn junction layer such that the transparent substrate is positioned in a superstrate configuration;
- and
- connecting the CdTe upper sub-cell and the lower sub-cell to each other in parallel, wherein the CdTe upper sub-cell and the lower sub-cell are voltage-matched.
Dependencies are inferred from the claim text.