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US 9,287,413 B2Granted
Junction gate field-effect transistor (JFET) and semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Chung Chen, Chi-Feng Huang
Life of this patent
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Abstract
A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions.
Claims20
An n-type junction gate field-effect transistor (NJFET), comprising:
- a substrate;
- a source region formed in the substrate, wherein the source region is an n-doped region;
- a drain region formed in the substrate, wherein the drain region comprises an n-well;
- a channel region formed in the substrate, the channel region connecting the source and drain regions, wherein the channel region is an n-doped region, and the n-well contacts the channel region;
- a deep n-well below the channel region, the deep n-well contacting the n-well of the drain region;
- at least one gate region formed in the substrate, the at least one gate region configured to cause a depletion in at least one of the source region or the drain region, wherein the at least one gate region is a p-doped region.
3 more elements
A semiconductor device, comprising:
- a substrate;
- and
- a transistor formed in the substrate, the transistor comprising a gate region, source and drain regions, and a channel region connecting the source and drain regions, wherein the gate region is separated from the drain region by a shallow trench isolation region;
- wherein, in a plan view of the substrate,
- at least one of the source region or the drain region extends around the gate region and the other of the at least one of the source region or the drain region;
- and
- the shallow trench isolation region extends around an entirety of the gate region.
4 more elements
A semiconductor device comprising:
- a source region in a substrate;
- a drain region in the substrate;
- a channel region in the substrate, wherein the channel region connects the source region and the drain region;
- a gate region in the substrate,
- wherein in a plan view of the substrate,
- the gate region and the drain region extend around the source region, the gate region being configured to cause a depletion region in at least one of the source region or the drain region,
- the gate region is separated from the at least one of the source region or the drain region by a shallow trench isolation region, and
- the shallow trench isolation region extends around an entirety of the gate region.
5 more elements
Dependencies are inferred from the claim text.